PDF HSP48908VC-20 Data sheet ( Hoja de datos )

Número de pieza	HSP48908VC-20
Descripción	Two Dimensional Convolver
Fabricantes	Intersil Corporation
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No Preview Available ! Data Sheet HSP48908 May 1999 File Number 2456.5 Two Dimensional Convolver The Intersil HSP48908 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. It eliminates the need for external data storage through the use of the on-chip row buffers which are programmable for row lengths up to 1024 pixels. There are Internal Register banks for storing two independent 3 x 3 ﬁlter kernels, thus facilitating the implementation of adaptive ﬁlters and multiple ﬁlter operations on the same data. The pixel data path also includes an on-chip ALU for performing real-time arithmetic and logical pixel point operations. Data is provided to the HSP48908 in a raster scan noninterlaced fashion, and is internally buffered on images up to 1024 pixels wide for the 3 x 3 convolution operation. Images with larger rows and convolution with larger kernel sizes can be accommodated by using external row buffers and/or multiple HSP48908s. Coefﬁcient and pixel input data are 8-bit signed or unsigned integers, and the 20-bit convolver output guarantees no overﬂow for kernel sizes up to 4 x 4. Larger kernel sizes can be implemented however, since the ﬁlter coefﬁcients will normally be less than their maximum 8-bit values. The HSP48908 is manufactured using an advanced CMOS process, and is a low power fully static design. The conﬁguration of the device is controlled through a standard microprocessor interface and all inputs/outputs are TTL compatible. Features • Single Chip 3 x 3 Kernel Convolution • Programmable On-Chip Row Buffers • DC to 32MHz Clock Rate • Cascadable for Larger Kernels and Images • On-Chip 8-Bit ALU • Dual Coefﬁcient Mask Registers, Switchable in a Single Clock Cycle • 8-Bit Signed or Unsigned Input and Coefﬁcient Data • 20-Bit Extended Precision Output • Standard µP Interface • Low Power CMOS Applications • Image Filtering • Edge Detection • Adaptive Filtering • Real Time Video Filter Ordering Information PART NUMBER HSP48908VC-20 HSP48908VC-32 HSP48908JC-20 HSP48908JC-32 HSP48908GC-20 TEMP. RANGE (oC) PACKAGE 0 to 70 100 Ld MQFP 0 to 70 100 Ld MQFP 0 to 70 84 Ld PLCC 0 to 70 84 Ld PLCC 0 to 70 84 Ld PGA PKG. NO. Q100x14x20 Q100x14x20 N84.1.15 N84.1.15 G84.A HSP48908GC-32 0 to 0 84 Ld PGA G84.A 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 1 page Block Diagram DATA DELAY DIN0 - 7 Z-1 Z-1 Z-1 Z-1 ALU CIN0 - 9 Z -1 ALU REGISTER HSP48908 r CASIO - 7 ROW BUFFER CASCADE MODE 2:1 r CASIO - 15 ROW BUFFER CASCADE MODE 22::11 Z-1 Z-1 Z-1 CASIO0 - 7 CONTROL LOGIC FRAME RESET OE CASIO - 15 Z-1 16 SHIFT A0 - 2 LD CS 3 ADDRESS DECODER Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 GH I D EF A BC Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 + CASCADE MODE Z-1 20 20 2:1 0 Z -1 ++ Z-1 Z-1 + Z -1 DOUTO - 19 CLK HOLD CLOCK GEN INTERNAL CLOCK 5 5 Page HSP48908 is being read synchronous to the internal clock. Therefore, care must be taken when modifying the convolver setup parameters during processing to avoid changing the contents of the registers near a rising edge of CLK. The required setup time relative to CLK is given by the Speciﬁcation TLCS. For example, in order to change the active Coefﬁcient Register from CREG0 to CREG1 during an active convolution operation, a write will be performed to the address for selecting CREG1 for internal processing (A2 -0 = 110). In order to provide proper uninterrupted operation, LD should be deasserted at least TLCS prior to the next rising edge of CLK. Failure to meet this setup time may result in unpredictable results on the output of the convolver for one clock cycle. Keep in mind that this requirement applies only to the case where changes are being made in the control logic during an active convolution operation. In a typical convolver conﬁguration routine, this speciﬁcation would not be applicable. TABLE 4. ADDRESS MAP CONTROL LOGIC ADDRESS MAP A2-0 FUNCTION 000 Load Row Length Register (RLR). 001 Load ALU Microcode Register (AMC). 010 Load Coefficient Register 0 (CREG0). 011 Load Coefficient Register 1 (CREG1). 100 Load Initialization Register (INT). 101 Select CREG0 for Internal Processing. 110 Select CREG1 for Internal Processing. 111 No Operation. Cascade I/O Cascade Input The cascade input lines (CASl0-15) have two primary functions. The ﬁrst is used to allow convolutions with kernel sizes larger than 3 x 3. This can be implemented by connecting the DOUT bus of one convolver to the cascade inputs of another. The second function is for convolution on images wider than 1024 pixels. This type of operation can be implemented by using external row buffers to supply the pixel input data to the CASl0-15 inputs. The cascade input functions are determined by Initialization Register bit 0. When this bit is set to a “0”, the cascade input data is added to the convolver output. In this manner, multiple convolvers can be used to implement larger kernel convolution. When Initialization Register bit 0 is “1”, the data on CASl0-15 is divided into two 8-bit portions and is sent to the 3 x 3 multiplier array (refer to Block Diagram). This mode of operation allows the use of external row buffers for convolution of images with row sizes larger than 1024. Examples of these conﬁgurations are given in the Operations Section of this speciﬁcation. The data on the cascade inputs (CASl0-15) can also be left shifted by 0, 2, 4, or 8 bits. The amount of shift is determined by bits 7 and 8 of the Initialization Register (See Table 3). CASl0-15 is shifted by the speciﬁed number of bits and is added to the 20-bit output DOUT 0-19. The shifting function provides a method for cascading multiple HSP48908s and allowing a selectable amount of output growth while maximizing the resolution of the convolver result. The cascade inputs can also be used as a simple way to add an offset to the convolved image. Bit 0 of the Conﬁguration Register would be set to ‘0’, and the desired offset placed on the CASl0-15 inputs. While multiple offsets can be used and changed during the convolution operation, note that the required data setup and hold times with respect to CLK (TDS and TDH) must be met. Cascade Output The cascade output lines (CASO0-7) are outputs from the second row buffer. Data at these outputs is the input pixel data delayed by two times the preprogrammed value in the Row Length Register. The cascade outputs are used to cascade multiple convolvers by connecting the cascade outputs of one device to the data inputs of another (see Operation Section). Control Signals HOLD The HOLD control input provides the ability to disable internal clock and stop all operations temporarily. HOLD is sampled on the rising edge of CLK and takes effect during the following clock cycle (refer to Figure 2). This signal can be used to momentarily ignore data at the input of the convolver while maintaining its current output data and operational state. CLK HOLD INTERNAL CLOCK FIGURE 2. HOLD OPERATION RESET The RESET signal initializes all internal ﬂip ﬂops and registers in the HSP48908. It is an asynchronous signal, and the convolver will remain in the reset state as long as RESET is asserted. On reset, all internal registers are set to zero or their default values, and all outputs are forced low. Following a reset, the default values in the internal registers will deﬁne the following mode of operation: internal row buffers used, line length = 1024, no input data delay, logical 11 11 Page

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