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PDF HSP45314VI Data sheet ( Hoja de datos )
| Número de pieza | HSP45314VI | |
| Descripción | CommLinkTM Direct Digital Synthesizer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
Data Sheet
HSP45314
May 2000 File Number 4820.2
CommLinkTM Direct Digital Synthesizer
The 14-bit HSP45314 provides a complete Direct Digital
Synthesizer (DDS) system in a single 48-pin LQFP package.
A 48-bit Programmable Carrier NCO (numerically controlled
oscillator) and a high speed 14-bit DAC (digital to analog
converter) are integrated into a stand alone DDS.
The DDS accepts 48-bit center and offset frequency control
information via a parallel processor interface. Modulation
control is provided by 3 external pins. The PH0 and PH1 pins
select phase offsets of 0, 90, 180 and 270 degrees, while the
ENOFR pin enables or zeros the offset frequency word to
the phase accumulator.
The parallel processor interface has an 8-bit write-only data
input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe
(WR), and a Write Enable (WE). The processor can update
all registers simultaneously by loading a set of master
registers, then transfer all master registers to the slave
registers by asserting the UPDATE pin.
Block Diagram
C(7:0)
A(3:0)
WR
WE
UPDATE
ENOFR
PH(1:0)
RESET
CLK
PHASE
ACCUM.
∑
SINE
WAVE
ROM
-
+
14 BIT
DAC
INT
REF
IN-
IN+
COMP1
COMP2
IOUTA
IOUTB
REFIO
REFLO
Features
• 125MSPS Output Sample Rate with 5V Digital Supply
• 100MSPS Output Sample Rate with 3.3V Digital Supply
• 14-bit DAC with Internal Reference
• Parallel Control Interface for Fast Tuning (50MSPS Control
Register Write Rate)
• 48-bit Programmable Frequency Control
• Small 48-pin LQFP package
Applications
• Programmable Local Oscillator
• FSK Modulation
• Direct Digital Synthesis
• Clock Generation
Ordering Information
PART
NUMBER
HSP45314VI
TEMP. RANGE
(oC) PACKAGE
PKG. NO.
-40 to 85 48 LQFP
Q48.7X7A
Pinout
48-PIN LQFP (Q48.7X7A
TOP VIEW
C2
C1
C0
ENOFR
DGND
CLK
DVDD
RESET
UPDATE
COMPOUT
REFLO
REFIO
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6
HSP45314
31
7 30
8 29
9 28
10 27
11 26
1213
14
15
16
17
18
19
20
21
22
23
25
24
A2
A3
PH0
PH1
DGND
DVDD
DGND
DGND
DGND
DGND
DVDD
DGND
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
CommLink™ is a trademark of Intersil Corporation.
1 page  
HSP45314
‘transmission line’, typically a spectrum analyzer,
oscilloscope, or the next function in the signal chain. The
necessity to have a 50Ω impedance looking back into the
transformer is negated if the DDS is only driving a short
trace. The output voltage compliance range does limit the
impedance that is loading the DDS output.
Ground Plane Considerations
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane. Pins 11 through 24 are analog pins,
while all of the others are digital.
Noise Reduction Considerations
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the power supply pins, AVDD
and DVDD. Also, the layout should be designed using
separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD. Additional filtering
of the power supplies on the board is recommended.
Power Supplies
The DDS will provide the best SFDR (Spurious Free
Dynamic Range) when using +5V analog and +5V digital
power supply. The analog supply must be +5V (±10%). The
digital supply can be either a +3.3V (±10%) or a +5V (±10%)
supply, or anything in between. The DDS is rated to
125MSPS when using a +5V digital supply. The maximum
clock is 100MSPS when using a +3.3V digital supply.
Improving SFDR
As was previously noted, using +5V power supplies provides
the best SFDR. Under some clock and output frequency
combinations, particularly when the fCLK/fOUT ratio is less
than 4, the user can improve SFDR even further by
connecting the COMP2 pin (19) of the DDS to the analog
power supply. The digital supply must be +5V if this option is
explored. Improvements as much as 6dBc in the SFDR-to-
Nyquist measurement were seen in the lab.
FSK Modulation
BFSK (Binary Frequency Shift Keying) can be done by
enabling and disabling the offset frequency (ENOFR pin).
Once the offset frequency has been written once, it can be
toggled with a latency of 14 CLK cycles.
M-ary FSK or GFSK can be done by continuously loading in
new frequency words.
Quadrature Local Oscillators
Two HSP45314s can be used as sine/cosine generators for
quadrature local oscillator applications. It is important to note
that the Phase Accumulator feedback needs to be zeroed in
both devices if it is desired that both DDSs restart with a
known phase, which is determined by the use of the phase
control pins, PH1 and PH0. To zero the phase accumulator,
pull bit 5 of address 13 low and then high again at the same
time in both devices.
3-5
5 Page 
Timing Diagrams
HSP45314
WE
ADDR
DATA
WRITE
CLK
UPDATE
ANALOG OUT
tWS
tAS
A0
tAH
A1
tWH
A2 A3 A4 A5
DON’T CARE
W0 W1
tDS tDH
W2 W3 W4 W5
6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD
DON’T CARE
DON’T CARE
DON’T CARE
tUS
tUD
tUL = 14 CLK RISING EDGES
OLD FREQ
NEW FREQ
FIGURE 2. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH)
WE
ADDR
DATA
WRITE
CLK
UPDATE
tWS
tAS tAH
A0 A1
tWH
A2 A3 A4 A5
DON’T CARE
W0 W1
tDS tDH
W2 W3 W4 W5
t = 6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD
DON’T CARE
DON’T CARE
DON’T CARE
tUL= 11 CLK RISING EDGES
ANALOG OUT
PREVIOUS FREQ
PARTIAL UPDATES
ENTIRE NEW FREQ
FIGURE 3. PARALLEL-LOAD METHOD 2, UPDATE ACTIVE WHILE LOADING REGISTERS (RESET = HIGH)
3-11
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