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PDF AS7C31025-15JI Data sheet ( Hoja de datos )
| Número de pieza | AS7C31025-15JI | |
| Descripción | 5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout) | |
| Fabricantes | ETC | |
| Logotipo |  |
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March 2001
AS7C1025
AS7C31025
®
5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)
Features
• AS7C1025 (5V version)
• AS7C31025 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 715 mW (AS7C1025) / max @ 12 ns (5V)
- 360 mW (AS7C31025) / max @ 12 ns (3.3V)
• Low power consumption: STANDBY
- 27.5 mW (AS7C1025) / max CMOS (5V)
- 1.8 mW (AS7C31025) / max CMOS (3.3V)
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
VCC
GND
Input buffer
A0
A1
A2
A3
A4
512×256×8
Array
A5 (1,048,576)
A6
A7
A8
I/O7
I/O0
32-pin TSOP II
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24
23
VCC
I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
Column decoder
Control
circuit
WE
OE
CE
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24 VCC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
AS7C1025
AS7C31025
AS7C1025
Maximum CMOS standby current
AS7C31025
AS7C1025-12
AS7C31025-12
12
3
130
100
5
5
AS7C1025-15
AS7C31025-15
15
4
85
85
5
5
AS7C1025-20
AS7C31025-20
20
5
80
80
5
5
Unit
ns
ns
mA
mA
mA
mA
Shaded areas contain advance information.
3/23/01; v.1.0
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
1 page  
®
Write cycle (over the operating range)11
Parameter
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
Symbol
tWC
tCW
tAW
tAS
tWP
tAH
tDW
tDH
tWZ
tOW
-12
Min Max
12 –
8–
8–
0–
8–
0–
6–
0–
–5
3–
-15
Min Max
15 –
12 –
12 –
0–
9–
0–
8–
0–
–5
3–
-20
Min Max
20 –
12 –
12 –
0–
12 –
0–
12 –
0–
–5
3–
Write waveform 1 ( WE controlled)10,11
Address
tWC
tAW
WE
tAS
tWP
DIN
tWZ
DOUT
tAH
tDW
Data valid
tOW
tDH
Write waveform 2 (CE controlled)10,11
tWC
tAW
Address
tAS tCW
CE
tWP
WE
tWZ
DIN
DOUT
tDW
Data valid
tAH
tDH
AS7C1025
AS7C31025
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns 4, 5
ns 4, 5
ns 4, 5
3/23/01; v.1.0
Alliance Semiconductor
P. 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AS7C31025-15JI.PDF ] | |
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