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PDF AS3588AQ Data sheet ( Hoja de datos )
| Número de pieza | AS3588AQ | |
| Descripción | DIGITAL TIME/SPACE CROSSPOINT SWITCH | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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Data Sheet
AS3588A
Austria Mikro Systeme International AG
Key Features
n 8-Line x 32 PCM Channel Inputs
n 8-Line x 32 PCM Channel Output
n 256 Ports Non Blocking Time/Space Crosspoint
Switch
n Single Power Supply of 5V
n Low Power Consumption
n Microprocessor Control Interface
n Open Drain Serial Outputs
n CMOS Process
n Simultaneous Connection/Disconnection under
Microprocessor Control
n Extraction/Insertion of Single PCM Channels
n Channel Zero Extraction
DIGITAL TIME/SPACE
CROSSPOINT SWITCH
General Description
AS3588A is designed for switching PCM channels
under microprocessor control in digital exchanges,
PBX or Central Office equipment. It provides a non
blocking digital switching matrix for up to 256x256
64 kbit/sec channels.
Each of the eight serial inputs and outputs consists of
32 64 kbit/sec channels multiplexed to/from a 2048
kbit/sec serial PCM bit stream.
Simultaneously it allows its controlling microprocessor
to read PCM output channels or to write to PCM
output channels.
Ordering Information
Part Number
Package
AS3588AP
40 Pin DIP
AS3588AQ
44 QFP
Block Diagramme
INP PCM0
INP PCM1
INP PCM2
INP PCM3
INP PCM4
INP PCM5
INP PCM6
INP PCM7
SERIAL
TO
PARALLEL
CONVERTER
CHANNEL 0
EXTRACTION
LOGIC
DATA MEMORY
256 X 8
DIN DOUT
AD
DM MUX
OD
MUX
PARALLEL
SERIAL
TO
CONVERTER
DOUT
CONNECTION
MEMORY AD
256 X 9
DIN
CM
MUX
TIME BASE
MICROPROCESSOR INTERFACE AND CONTROL LOGIC
OUT PCM0
OUT PCM1
OUT PCM2
OUT PCM3
OUT PCM4
OUT PCM5
OUT PCM6
OUT PCM7
SYNC
CLOCK
RES A1 S1 A2 S2 CS1 CS2 WR RD C/D DR
D0......D7
Figure 1: Block Diagramme
Rev. 3.1
Page 1 of 15
July 1999
1 page  
Data Sheet
of two data bytes and one command byte. Byte one
and two contain information about the PCM output line
and the PCM output channel and act as address
pointer to the specific connection memory location.
The command instruction is only executed if AS3588A
is selected by CS1=CS2=0 and if the condition A1=S1
and A2=S2 is met. If the device is only selected by
CS1 and CS2. this command is not executed and DR
remains high. If the instruction code was found to be
invalid, DR is driven low until a valid instruction code is
supplied; the registers are not modified.
3) BYTE INSERTION INTO A PCM OUTPUT
CHANNEL / CHANNEL DISCONNECTION
This function inserts a single byte from the micropro-
cessor into a PCM output channel. The control infor-
mation from the microprocessor consists of four data
bytes and one command byte. Byte one and two
contain the message byte from the microprocessor
which is stored in a connection memory location. Byte
three and four contain information about the PCM
output line and the PCM output channel and act as
address to the specific connection memory location
where the message byte that is contained in byte1 and
byte 2 is stored. If AS3588A is selected by CS1, CS2
and if the condition A1=S1 and A2=S2 is met, the
command instruction is executed as defined. If the
device is selected by CS1 and CS2 only this command
will perform a disconnect function on the specific
output channel. If the instruction code was found to be
invalid, DR is driven low until a valid instruction code is
supplied; the registers are not modified.
4) PCM OUTPUT CHANNEL EXTRACTION
This function extracts a specific output channel and
transfers it to the microprocessor bus. PCM input
channels can be extracted by connecting the channels
to output channels with instruction 1. The control infor-
mation from the microprocessor consists of two data
bytes and one command byte. Byte one and two
contain information about the PCM output line and the
PCM output channel. The extracted channel is stored
in the OR1 register. The command instruction is only
executed if AS3588A is selected by CS1=CS2=0 and
if the condition A1=S1 and A2=S2 is met. If the device
is only selected by CS1 and CS2. this command is not
executed and DR remains high.
If the instruction code was found to be invalid, DR is
driven low until a valid instruction code is supplied; the
registers are not modified.
5) TRANSFER OF A CONNECTION MEMORY
LOCATION
This function allows the access of the contents of a
connection memory location associated to a specific
PCM output channel and transfers it to the micropro-
cessor bus. The control information from the micropro-
cesor consists of two data bytes and one command
byte. Byte one and two contain information about the
PCM output line and the PCM output channel. The
connection memory bits C7 to C0 are stored in register
AS3588A
OR1, C8 is stored in register OR2. If C8=0 the
remaining eight bits contain information about the con-
nected PCM input channel. If C8=1, the remaining bits
can be all log. "1" if the output channel is not con-
nected to an input channel and if it was not modified
by the microprocessor. If C8=1 but the remaining bits
are not all set to log. "1" they contain a message byte
from an active output channel which was loaded by the
byte insertion instruction 3. DR goes low for two clock
cycles in that case. The command instruction is exe-
cuted if AS3588A is selected by CS1=CS2=0. If the in-
struction code was found to be invalid, DR is driven
low until a valid instruction code is supplied; the regis-
ters are not modified.
6) TRANSFER OF 0 CHANNEL PCM DATA FROM
SELECTED PCM INPUTS
This function is used to extract the contents of channel
0 of the PCM inputs which do not contain "01" in the
two most significant bits. The control information from
the microprocessor consists of two data bytes and one
command byte. Byte one and two contain information
about the PCM input selection mask byte. The
contents of channel 0 are available from the OR1
register from which the microprocessor can transfer
them by successive reads from the same register. To
enable instruction 6 it is necessary to read register
OR2. This is because instruction 6, used between
other short instructions of type 1 to 5 , must have a
lower priority and can be enabled only after the short
instructions have been completed. Instruction 6 nor-
mally has a long process and a special flow: First a
not-all-zero mask field is stored in the "expected
messages" register and in another "background" reg-
ister. A logic "1" means an input bus enabling condi-
tion, a log. "0" means an input bus disabling condition.
This operation starts the second phase of instruction 6
which is called "channel 0 extraction" and is repeated
at the beginning of any new time frame. At the
beginning of the time frame a new copy of activated
channels to be extracted is made from the
"background register"' and put in the "expected mes-
sages'' register. In addition the latter register is modi-
fied to indicate the exact number of messages that
have arrived. The term messages covers any input 0
channel data with starting sequence different from
"01". Using this signature the number of expected
messages can be reduced to correspond to the
number of effective messages. If and only if the
residual number is different from zero will the device
start the extraction protocol at the end of the current
routine. The procedure is as follows:
The DR output is pulsed low for two clock cycles as in-
terrupt request to the microprocessor and OR2 is
loaded with the total number of active channels to be
extracted. The transfer of OR2 content to the micro-
processor continues the extraction which consists of
repeated steps of OR1 and OR2 loading indicating re-
spectively the message and the incoming bus number.
Rev. 3.1
Page 5 of 15
July 1999
5 Page 
Data Sheet
AS3588A
PCM Timing Characteristics (Figure 4 ): Operation over recommended temperature and voltage range
Symbol Parameter
Condition
Min.
Typ.*
Max. Units
tSPCM
PCM IN Setup Time
10 ns
tHPCM
PCM IN Hold Time
45 ns
tPDLPCM PCM OUT Delay Time
CL=50pF, RL=2k½
45
ns
tPDHPCM PCM OUT Delay Time
CL=50pF, RL=2k½
200
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing
ns
CLOCK
12
8
SYNC
tSPCM tHPCM
INP PCM
MSB
tPDHPCM
D
tPDLPCM
D
LSB
OUT PCM
MSB
D
D LSB
Figure 4. PCM Timing
Reset Timing Characteristics (Figure 5 ): Operation over recommended temperature and voltage range
Symbol Parameter
Condition
Min.
Typ.*
Max. Units
tSLRES Reset Low Setup Time
100 ns
tHLRES Reset Low Hold Time
50 ns
tSHRES Reset High Setup Time
90 ns
tWHRES Reset High Level Width
tCK
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing
ns
CLOCK
RESET
tHLRES
tSLRES
tSHRES
tWHRES
Figure 5 Reset Timing
Rev. 3.1
Page 11 of 15
July 1999
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AS3588AQ.PDF ] | |
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