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PDF EV8AQ165A Data sheet ( Hoja de datos )
| Número de pieza | EV8AQ165A | |
| Descripción | QUADRUPLE Analog to Digital Converter | |
| Fabricantes | e2v | |
| Logotipo |  |
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Datasheet
EV8AQ165A
QUADRUPLE Analog to Digital Converter High
Bandwith, Low power, Low input Swing QUAD
8-bit 1.25 GSps ADC operting up to 5 GSps
Main Features
• Quad ADC with 8-bit Resolution using e2v Proprietary Analog input Cross-point Switch
– 1.25 GSps Sampling Rate in 4-channel Mode
– 2.5 GSps Sampling Rate in 2-channel Mode
– 5 GSps Sampling Rate in 1-channel Mode
– Built-in four-by-four Cross Point Switch
• Single 2.5 GHz Differential Symmetrical Input Clock
• 250 mVpp Analog Input (Differential AC or DC Coupled)
• ADC Master Reset (LVDS)
• Double Data Rate Output Protocol
• LVDS Output Format
• Digital Interface (SPI) with Reset Signal:
– Channel Mode Selection
– Selectable Bandwidth (2 Available Settings)
– Gain, Offset, Phase Control
– Standby Mode (Full or Partial)
– Binary or Gray Coding Selection
– Test Modes (Ramp, Flashing "1")
• Power Supplies: 3.3V & 1.8V
• Reduced Clock induced Transients on Power Supply Pins due to BiCMOS Silicon Technology
• Power Dissipation: 1.4W per Channel
• EBGA380 Package (RoHS & non RoHS, 1.27 mm Pitch)
Performance
• Selectable Full Power Input Bandwidth (–3 dB) up to 3.2 GHz (4-2-1 Channel Mode)
• Band Flatness: ±0.5 dB from DC to 30% of Full Power Input Bandwidth
• Channel-To-Channel Isolation: > 60 dB
• 4-channel Mode (Fsampling = 1.25 GSps, –1 dBFS)
– Fin = 100 MHz (Bandwidth 1 GHz): ENOB = 7.1 bit, SFDR = 47 dBc, SNR = 45 dB, DNL = 0.35 LSB, INL = ±0.5 LSB
– Fin = 620 MHz (Full Bandwidth): ENOB = 7.0 bit, SFDR = 47 dBc, SNR = 44.5 dB
– Fin = 1.2 GHz ( Full Bandwidth): ENOB = 6.7 bit, SFDR = 47 dBc, SNR = 42.5 dB
• 2-channel or 1-channel Mode (Fsampling = 2.5 or 5 GSps, Fin = 620 MHz, –1 dBFS)
– Fin = 620 MHz (Full Bandwidth): ENOB = 7.0 bit, SFDR = 48 dBc, SNR = 44 dB
– Fin = 1.2 GHz ( Full Bandwidth): ENOB = 6.7 bit, SFDR = 48 dBc, SNR = 42 dB
• BER: 10-16 at Full Speed
• Latency: 4-channel: 6.5 Clock Cycles
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for the latest version of the datasheet
e2v semiconductors SAS 2014
1119A–BDC–03/14
1 page  
EV8AQ165A
Figure 2-5. 2-channel Mode Configuration (Analog Input B and Analog Input D)
CLK
(2.5 GHz)
Inverted
1.25 GHz
Clock
Circuit
In-
phase
1.25
GHz
ADC A
1.25
GSps
ADC B
1.25
GSps
ADC C
1.25
GSps
ADC D
1.25
GSps
BAI, BAIN
DAI, DAIN
Note: Refer to Figure 3-2 on page 16
Figure 2-6. 1-channel Mode Configuration
CLK
(2.5 GHz)
Clock
Circuit
ADC A
1.25
GSps
ADC B
1.25
GSps
In-phase
1.25 GHz
Inverted
1.25 GHz
270˚ phase-shifted
1.25 GHz
90˚ phase-shifted
1.25 GHz
ADC C
1.25
GSps
ADC D
1.25
GSps
AAI, AAIN or BAI, BAIN or CAI, CAIN or DAI, DAIN
Notes:
1. Refer to Figure 3-3 on page 17
2. For simplification purpose of the timer circuit, the temporary order of ports for sampling is A C B D,
therefore sampling order at output port is as follows:
A: N, N + 4, N + 8, N + 12…
C: N + 1, N + 5, N + 9…
B: N + 2, N + 6, N + 10…
D: N + 3, N + 7, N + 11…
The T/H (Track and Hold) is located after the Cross Point Switch and before the ADC cores. This block is
used to track the data when the internal sampling clock is low and to hold the data when the internal
sampling clock is high. This stage has a gain of 2.
The ADC cores are all the same for the four ADCs. They include a quantifier block as well as a fast logic
block composed of regenerating latches and the Binary/Gray decoding block.
The SPI block provides the digital interface for the digital controls of the ADCs. All the functions of the
ADC are contained in the SPI registers and controlled via this SPI (channel selection, standby mode,
Binary or Gray coding, Offset Gain and Phase adjust..).
The Output buffers are LVDS compatible. They should be terminated using a 100 external termination
resistor.
e2v semiconductors SAS 2014
1119A–BDC–03/14
5
5 Page 
EV8AQ165A
Table 3-5. Dynamic Characteristics
Parameter
Symbol Test Level Min Typ Max
AC ANALOG INPUTS
Full Power Input Bandwidth in Full mode (BW = “1” in 0x01 register)
Full Power Input Bandwidth in Nominal mode (BW = “0” in 0x01
register, default mode)
FPBW
4
3.2
1.5
Gain Flatness (±0.5 dB in full band mode setting BW = “1” in 0x01
register)
GF
4
1.5
Input Voltage Standing Wave Ratio up to 3 GHz
VSWR
4
2.13
Crosstalk (Fin = 620 MHz)
4 60
Dynamic Performance – 4-Channel Mode (Fsampling = 1.25 GSps, Vin = –1 dBFS) for each channel (after calibration)
Effective Number Of Bits
Fs = 1.25 GSps Fin = 100 MHz
Fs = 1.25 GSps Fin = 620 MHz
Fs = 1.25 GSps Fin = 1200 MHz
7.1 7.3
ENOB
1. 4
7.0 7.2
6.7 6.9
Signal to Noise Ratio
Fs = 1.25 GSps Fin = 100 MHz
Fs = 1.25 GSps Fin = 620 MHz
Fs = 1.25 GSps Fin = 1200 MHz
SNR
45 46
1. 4
44.5 45
42.5 43
Total Harmonic Distortion (9 Harmonics)
Fs = 1.25 GSps Fin = 100 MHz
Fs = 1.25 GSps Fin = 620 MHz
Fs = 1.25 GSps Fin = 1200 MHz
46 54
|THD|
1. 4
46 53
46 53
Spurious Free Dynamic Range
Fs = 1.25 GSps Fin = 100 MHz
Fs = 1.25 GSps Fin = 620 MHz
Fs = 1.25 GSps Fin = 1200 MHz
|SFDR|
1. 4
47 57
47 55
47 53
Two tone third order intermodulation distortion
Fs = 1.25 GSps
Fin1 = 490 MHz ; Fin2 = 495 MHz [–7dBFS]
|IMD3|
4
53
Dynamic Performance – 2 Channel Mode at 1.25 Gsps or 1-Channel Mode at 2.5 GSps, –1 dBFS (after calibration)
Effective Number Of Bits
Fs = 2.5 GSps Fin = 100 MHz
Fs = 2.5 GSps Fin = 620 MHz
Fs = 2.5 GSps Fin = 1200 MHz
7.3
ENOB
1. 4
7.0 7.2
6.7 7.0
Signal to Noise Ratio
Fs = 2.5 GSps Fin = 100 MHz
Fs = 2.5 GSps Fin = 620 MHz
Fs = 2.5 GSps Fin = 1200 MHz
SNR
46
1. 4
44 45
42 43
Total Harmonic Distortion (9 Harmonics)
Fs = 2.5 GSps Fin = 100 MHz
Fs = 2.5 GSps Fin = 620 MHz
Fs = 2.5 GSps Fin = 1200 MHz
54
|THD|
1. 4
48 54
46 53
Unit
GHz
GHz
GHz
dB
Bit
dB
dB
dBc
dBFS
Bit
dB
dB
Note
(1)
(2)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
e2v semiconductors SAS 2014
1119A–BDC–03/14
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EV8AQ165A.PDF ] | |
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