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PDF TM090JDH01 Data sheet ( Hoja de datos )
| Número de pieza | TM090JDH01 | |
| Descripción | Display Module | |
| Fabricantes | AVIC | |
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SHANGHAI AVIC OPTOELECTRONICS
CO-Q/S1037-2012
MODEL NO. :
ISSUED DATE:
VERSION :
TM090JDH01
2012-7-18
Ver. 2.0
□Preliminary Specification
■Final Product Specification
Customer :
Approved by
Notes
SHANGHAI AVIC Confirmed :
Prepared by
Ye Chen
2012/7/18
Checked by
-
Approved by
Hyman Chen
2012/7/18
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of SHANGHAI AVIC OPTOELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI AVIC OPTOELECTRONICS Corporation.
Page 1 of 25
1 page  
SHANGHAI AVIC OPTOELECTRONICS
CO-Q/S1037-2012
2 Input/Output Terminals
2.1 CN1 of FPC
No
Symbol
I/O
1
VDD
P
2
GND
P
3
Reset
I
4 SCL I
5
SDA
I/O
6 INT O
7 NC
8 NC
9
GND
P
10
GND
P
11
GND
P
12 NC
Description
Power supply input for C-TP
Ground for C-TP
Reset C-TP
Clock pin for I2C communication
Data pin for I2C communication
Interrupt pin
--
--
Ground
Ground
Ground
--
Comment
Notes1
13
VDD
P
Power Voltage for digital circuit
14
VDD
P
Power Voltage for digital circuit
15 NC
--
16 Reset I
Global reset pin
Standby mode, Normally pulled high
17
STBYB
I
STBYB = “1”, normal operation
STBYB = “0”, timing controller, sourcedriver will
turn off, all output are High-Z
18
GND
P
Ground
19
RXIN0-
I
- LVDS differential data input
20
RXIN0+
I
+ LVDS differential data input
21
GND
P
Ground
22
RXIN1-
I
- LVDS differential data input
23
RXIN1+
I
+ LVDS differential data input
24
GND
P
Ground
25
RXIN2-
I
- LVDS differential data input
26
RXIN2+
I
+ LVDS differential data input
27
GND
P
Ground
28
RXCLKIN-
I
- LVDS differential clock input
29
RXCLKIN+
I
+ LVDS differential clock input
30
GND
P
Ground
31
RXIN3-
I
- LVDS differential data input
32
RXIN3+
I
+ LVDS differential data input
33
GND
P
Ground
34 NC
--
35 NC
--
36
GND
P
Ground
37 NC
--
38
DIMO
O Backlight CABC controller signal output
39
SELB
I
6bit/8bit mode select
Notes 2
40
AVDD
P
Power for Analog Circuit
The information contained herein is the exclusive property of SHANGHAI AVIC OPTOELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI AVIC OPTOELECTRONICS Corporation.
Page 5 of 25
5 Page 
SHANGHAI AVIC OPTOELECTRONICS
5 Timing Chart
5.1 Input Clock and Data Timing
CO-Q/S1037-2012
Input Timing diagram:
The information contained herein is the exclusive property of SHANGHAI AVIC OPTOELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI AVIC OPTOELECTRONICS Corporation.
Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet TM090JDH01.PDF ] | |
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