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PDF ISL6329 Data sheet ( Hoja de datos )
| Número de pieza | ISL6329 | |
| Descripción | Dual PWM Controller Powering AMD SVI Split-Plane Processors | |
| Fabricantes | Intersil | |
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Dual PWM Controller Powering AMD SVI Split-Plane
Processors
ISL6329
The ISL6329 dual PWM controller delivers high efficiency and
tight regulation from two synchronous buck DC/DC converters.
The ISL6329 supports power control of AMD processors, which
operate from a serial VID interface (SVI). The dual output
ISL6329 features a multiphase controller to support the Core
voltage (VDD) and a single phase controller to power the
Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-six-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in layout
and reduces the number of external components in the
multi-phase section. A single phase PWM controller with
integrated driver provides a second precision voltage regulation
system for the Northbridge portion of the processor. This
monolithic, dual controller with integrated driver solution
provides a cost and space saving power management solution.
For applications that benefit from load line programming to reduce
bulk output capacitors, the ISL6329 features temperature
compensated output voltage droop. The multiphase portion also
includes advanced control loop features for optimal transient
response to load application and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current balance.
Dual edge modulation is another unique feature, allowing for
quicker initial response to high di/dt load transients.
The ISL6329 supports Power Savings Mode by dropping the
number of phases to one or two when the PSI_L bit is set. For
even greater power efficiency, diode emulation and gate voltage
optimization are implemented in PSI mode.
Features
• Processor Core Voltage Via Integrated Multiphase Power
Conversion
• Configuration Flexibility
- 1 or 2-Phase Operation with Internal Drivers
- 3,4,5 or 6-Phase Operation with External PWM Drivers
• PSI_L Support
- Phase Shedding for Improved Efficiency at Light Load
- Diode Emulation in PSI mode
- Gate Voltage Optimization
• I2C Interface with 8 Selectable Addresses
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
- Temperature Compensated
• Serial VID Interface Handles up to 3.4MHz Clock Rates
• Two Level Overcurrent Protection Allows for High Current
Throttling (IDD_SPIKE)
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Pb-Free (RoHS Compliant)
April 19, 2011
FN7800.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Pin Configuration
ISL6329
ISL6329
(60 LD QFN)
TOP VIEW
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46
COMP_NB 1
FB_NB 2
VSEN_NB 3
DRPCTRL 4
SVC 5
SVD 6
VDDIO 7
SCL 8
SDA 9
VCC 10
RSVD 11
OFS 12
61
GND
45 PWM4
44 PWM5
43 PWM6
42 PWROK
41 VDDPWRGD
40 PHASE1
39 UGATE1
38 BOOT1
37 LGATE1
36 GVOT
35 LGATE2
34 BOOT2
OCP 13
TCOMP1 14
TCOMP2 15
33 UGATE2
32 GND
31 EN
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Functional Pin Descriptions
PIN NAME
COMP_NB
FB_NB
VSEN_NB
DRPCTRL
SVC
SVD
VDDIO
SCL
PIN NUMBER
1
2
3
4
5
6
7
8
DESCRIPTION
Output of the internal error amplifier for the Northbridge regulator.
Inverting input to the internal error amplifier for the Northbridge regulator.
Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor tied to ground: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop
On, Core Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
Serial VID clock input from the AMD processor.
Serial VID data bi-directional signal to and from the master device on AMD processor.
Reference voltage for the SVI communication bus. Connect this pin to the system VDDIO and decouple
using a quality 0.1μF ceramic capacitor.
Connect this pin to the clock signal for the I2C bus, which is a logic level input signal. The clock signal
tells the controller when data is available on the I2C bus.
5 FN7800.0
April 19, 2011
5 Page 
ISL6329
Electrical Specifications Boldface limits apply over the operating temperature range. (Continued)
POWER GOOD
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 7) TYP (Note 7) UNITS
Overvoltage Threshold
Undervoltage Threshold
Power Good Hysteresis
OVERVOLTAGE PROTECTION
VSEN Rising
VSEN Falling
VDAC +
220mV
VDAC +
325mV
V
VDAC -
345mV
VDAC -
190mV
mV
50 mV
OVP Trip Level
OVP Lower Gate Release Threshold
VDAC = 1.1V
SWITCHING TIME (Note 6) [See “Timing Diagram” on page 12]
1.75
0.35
1.79
1.85
V
V
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Non-overlap
LGATE Turn-On Non-overlap
GATE DRIVE RESISTANCE (Note 6)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
SVI INTERFACE
SVC, SVD Input HIGH (VIH)
SVC, SVD Input LOW (VIL)
Schmitt Trigger Input Hysteresis
SVD Low Level Output Voltage
SVC, SVD Leakage
I2C INTERFACE
tRUGATE; VPVCC = 8V, 3nF Load, 10% to 90%
tRLGATE; VPVCC = 8V, 3nF Load, 10% to 90%
tFUGATE; VPVCC = 12V, 3nF Load, 90% to 10%
tFLGATE; VPVCC = 12V, 3nF Load, 90% to 10%
tPDHUGATE; VPVCC = 12V, 3nF Load, Adaptive
tPDHLGATE; VPVCC = 12V, 3nF Load, Adaptive
26
18
18
12
10
10
ns
ns
ns
ns
ns
ns
VPVCC = 12V, 15mA Source Current
VPVCC = 12V, 15mA Sink Current
VPVCC = 12V, 15mA Source Current
VPVCC = 12V, 15mA Sink Current
2.5 Ω
2.0 Ω
1.6 Ω
1.1 Ω
Percentage of VVDDIO
Percentage of VVDDIO
Percentage of VVDDIO
511Ω Resistor to 1.8V
70 %
30 %
15 20 25 %
0.4 V
±5 μA
SCL, SDA Input HIGH (VIH)
1.8 V
SCL, SDA Input LOW (VIL)
1.0 V
Schmitt Trigger Input Hysteresis
0.18
0.5 V
SDA Low Level Output Voltage
1kΩ Resistor to 3.3V
0.4 V
SCL, SDA Leakage
±5 μA
NOTES:
6. Limits should be considered typical and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11 FN7800.0
April 19, 2011
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL6329.PDF ] | |
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