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PDF CY7C65642 Data sheet ( Hoja de datos )
| Número de pieza | CY7C65642 | |
| Descripción | Very Low Power USB 2.0 TetraHub Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C65642
HX2VL – Very Low Power USB 2.0
TetraHub™ Controller
HX2VL – Very Low Power USB 2.0 TetraHub™ Controller
Features
■ High-performance, low-power USB 2.0 hub, optimized for
low-cost designs with minimum bill-of-material (BOM).
■ USB 2.0 hub controller
❐ Compliant with USB2.0 specification, TID# 30000059
❐ Up to four downstream ports support
❐ Downstream ports are backward compatible with FS, LS
❐ Multiple translator (TT), one per downstream port for
maximum performance.
■ Very low-power consumption
❐ Supports bus-powered and self-powered modes
❐ Auto switching between bus-powered and self-powered
❐ Single MCU with 2 K ROM and 64 byte RAM
❐ Lowest power consumption.
■ Highly integrated solution for reduced BOM cost
❐ Internal regulator – single power supply 5 V required.
❐ Provision of connecting 3.3 V with external regulator.
❐ Integrated upstream pull-up resistor
❐ Integrated pull-down resistors for all downstream ports
❐ Integrated upstream/downstream termination resistors
❐ Integrated port status indicator control
❐ 12-MHz +/-500 ppm external crystal with drive level 600 W
(integrated PLL) clock input with optional 27/48-MHz
oscillator clock input.
❐ Internal power failure detection for ESD recovery
■ Downstream port management
❐ Support individual and ganged mode power management
❐ Overcurrent detection
❐ Two status indicators per downstream port
■ Maximum configurability
❐ VID and PID are configurable through external EEPROM
❐ Number of ports, removable/non-removable ports are
configurable through EEPROM and I/O pin configuration
❐ I/O pins can configure gang/individual mode power
switching, reference clock source and polarity of power
switch enable pin
❐ Configuration options also available through mask ROM
■ Available in space saving 48-pin TQFP (7 × 7 mm) and 28-pin
QFN (5 × 5 mm) packages
■ Supports 0 C to +70 C temperature range
Block Diagram
12/27/48
MHz
OSC-in
OR 12
MHz
Crystal
D+ D-
USB 2.0 PHY
PLL
USB Upstream Port
Hub Repeater
Serial
Interface
Engine
HS USB
Control Logic
MCU
RAM ROM
Transaction Translator x 4
Routing Logic
1.8 V Regulator
3.3 V
I2C /
SPI
5 V i/p (for internal
regulator)
NC (for external regulator)
3.3 V i/p (with ext. reg. & 28-QFN
NC (with ext. reg. & 48-TQFP)
3.3 V o/p (for int. reg.)
USB Downstream Port 1
USB 2.0
PHY
Port
Control
USB Downstream Port 2
USB 2.0
PHY
Port
Control
USB Downstream Port 3
USB 2.0
PHY
Port
Control
USB Downstream Port 4
USB 2.0
PHY
Port
Control
D+ D-
LED D+ D-
LED D+ D-
LED D+ D-
LED
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-65659 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 7, 2016
1 page  
CY7C65642
Functional Overview
The Cypress CY7C65642 USB 2.0 Hubs are low-power hub
solutions for USB which provide maximum transfer efficiency
with no TT multiplexing between downstream ports. The
CY7C65642 USB 2.0 Hubs integrate 1.5 k upstream pull-up
resistors for full speed operation and all downstream 15 k
pull-down resistors and series termination resistors on all
upstream and downstream D+ and D– pins. This results in
optimization of system costs by providing built-in support for the
USB 2.0 specification.
System Initialization
On power up, CY7C65642 has an option to enumerate from the
default settings in the mask ROM or from reading an external
EEPROM for configuration information. At the most basic level,
this EEPROM has the Vendor ID (VID) and the Product ID (PID),
for the customer's application. For more specialized
applications, other configuration options can be specified. See
EEPROM Configuration Options on page 14 for more details.
CY7C65642 verifies the checksum before loading the EEPROM
contents as the descriptors.
Enumeration
CY7C65642 enables the pull-up resistor on D+ to indicate its
presence to the upstream hub, after which a USB Bus Reset is
expected. After a USB Bus Reset, CY7C65642 is in an
unaddressed, unconfigured state (configuration value set to’0’).
During the enumeration process, the host sets the hub's address
and configuration. After the hub is configured, the full hub
functionality is available.
Multiple Transaction Translator Support
After TetraHub is configured in a high speed system, it is in single
TT mode. The host may then set the hub into multiple TT mode
by sending a SetInterface command. In multiple TT mode, each
full speed port is handled independently and thus has a full
12 Mbps bandwidth available. In Single TT mode, all traffic from
the host destined for full or low-speed ports are forwarded to all
of those ports. This means that the 12 Mbps bandwidth is shared
by all full and low-speed ports.
Upstream Port
The upstream port includes the transmitter and the receiver state
machine. The transmitter and receiver operate in high speed and
full speed depending on the current hub configuration. The
transmitter state machine monitors the upstream facing port
while the Hub Repeater has connectivity in the upstream
direction. This machine prevents babble and disconnect events
on the downstream facing ports of this hub from propagating and
causing the hub to be disabled or disconnected by the hub to
which it is attached.
Downstream Ports
The CY7C65642 supports a maximum of four downstream ports,
each of which may be marked as usable or removable in the
EEPROM configuration, see EEPROM Configuration Options on
page 14. Additionally, it can also be configured by pin strapping,
see Pin Configuration Options on page 15.
Downstream D+ and D– pull-down resistors are incorporated in
CY7C65642 for each port. Before the hubs are configured, the
ports are driven Single Ended Zero, ((SE0) where both D+ and
D– are driven low) and are set to the unpowered state. When the
hub is configured, the ports are not driven and the host may
power the ports by sending a SetPortPower command for each
port. After a port is powered, any connect or disconnect event is
detected by the hub. Any change in the port state is reported by
the hubs back to the host through the Status Change Endpoint
(endpoint 1). On receipt of SetPortReset request for a port with
a device connected, the hub does as follows:
■ Performs a USB Reset on the corresponding port
■ Puts the port in an enabled state
■ Enables babble detection after the port is enabled.
Babble consists of a non idle condition on the port after EOF2. If
babble is detected on an enabled port, that port is disabled. A
ClearPortEnable request from the host also disables the
specified port.
Downstream ports can be individually suspended by the host
with the SetPortSuspend request. If the hub is not suspended, a
remote wakeup event on that port is reflected to the host through
a port change indication in the Hub Status Change Endpoint. If
the hub is suspended, a remote wakeup event on this port is
forwarded to the host. The host may resume the port by sending
a ClearPortSuspend command.
Power Switching
The CY7C65642 includes interface signals for external port
power switches. Both ganged and individual (per-port)
configurations are supported by pin strapping, see Pin
Configuration Options on page 15.
After enumerating, the host may power each port by sending a
SetPortPower request for that port. Power switching and
overcurrent detection are managed using respective control
signals (PWR#[n] and OVR#[n]) which are connected to an
external power switch device. Both High/Low enabled power
switches are supported and the polarity is configured through
GPIO setting, see Pin Configuration Options on page 15.
Overcurrent Detection
The OVR#[n] pins of the CY7C65642 series are connected to the
respective external power switch’s port overcurrent indication
(output) signals. After detecting an overcurrent condition, hub
reports overcurrent condition to the host and disables the
PWR#[n] output to the external power device. OVR#[n] has a
setup time of 20 ns. It takes 3 to 4 ms from overcurrent detection
to deassertion of PWR#[n]
Port Indicators
The USB 2.0 port indicators are also supported directly by
CY7C65642. According to the specification, each downstream
port of the hub optionally supports a status indicator. The
presence of indicators for downstream facing ports is specified
by bit 7 of the wHubCharacteristics field of the hub class
descriptor. The default CY7C65642 descriptor specifies that the
port indicators are supported. The CY7C65642 port indicators
has two modes of operation: automatic and manual.
Document Number: 001-65659 Rev. *H
Page 5 of 26
5 Page 
CY7C65642
Pin Definitions (continued)
48-pin TQFP Package
Pin Name
Pin No.
Downstream Port 4
DD–[4]
21
DD+[4]
22
AMBER[4]
SET_PORT_NUM1
24
GREEN[4]
FIXED_PORT4
23
OVR#[4]
28
PWR#[4]
29
Type [1]
I/O/Z
I/O/Z
O(RDN)
I(RDN)
O(RDN)
I(RDN)
I(RUP)
O/Z
Description
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for Amber LED. Port Indicator Support.
SET_PORT_NUM1. Used to set port numbering along with SET_PORT_NUM2.
Refer “Pin Configuration Options” on page 15
LED. Driver output for Green LED. Port Indicator Support.
FIXED_PORT4. At POR used to set Port4 as non removable port. Refer Pin
Configuration Options on page 15.
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input.
Power Switch Driver Output. Default is Active LOW.
Note: The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high, unless a separate
circuit is designed to support logic high. Disconnect after 60 ms of power-on reset (POR), when these pins are reconfigured as
outputs.
Document Number: 001-65659 Rev. *H
Page 11 of 26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet CY7C65642.PDF ] | |
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