PDF CY7C64713 Data sheet ( Hoja de datos )

Número de pieza	CY7C64713
Descripción	Full Speed USB Peripheral Controller
Fabricantes	Cypress Semiconductor
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CY7C64713 EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller Features ■ Single chip integrated USB transceiver, SIE, and enhanced 8051 microprocessor ■ Fit, form, and function upgradable to the FX2LP (CY7C68013A) ❐ Pin compatible ❐ Object code compatible ❐ Functionally compatible (FX1 functionality is a subset of the FX2LP) ■ Draws no more than 65 mA in any mode, making the FX1 suitable for bus powered applications ■ Software: 8051 runs from internal RAM, which is: ❐ Downloaded using USB ❐ Loaded from EEPROM ❐ External memory device (128 pin configuration only) ■ 16 KB of on-chip code/data RAM ■ Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints ❐ Buffering options: double, triple, and quad ■ Additional programmable (BULK/INTERRUPT) endpoint 64-byte ■ 8- or 16-bit external data interface ■ Smart media standard ECC generation ■ GPIF ❐ Allows direct connection to most parallel interfaces; 8- and 16-bit ❐ Programmable waveform descriptors and configuration registers to define waveforms ❐ Supports multiple ready (RDY) inputs and Control (CTL) outputs ■ Integrated, industry standard 8051 with enhanced features: ❐ Up to 48 MHz clock rate ❐ Four clocks for each instruction cycle ❐ Two USARTS ❐ Three counters or timers ❐ Expanded interrupt system ❐ Two data pointers ■ 3.3 V operation with 5 V tolerant inputs ■ Smart SIE ■ Vectored USB interrupts ■ Separate data buffers for the setup and DATA portions of a CONTROL transfer ■ Integrated I2C controller, running at 100 or 400 KHz ■ 48 MHz, 24 MHz, or 12 MHz 8051 operation ■ Four integrated FIFOs ❐ Brings glue and FIFOs inside for lower system cost ❐ Automatic conversion to and from 16-bit buses ❐ Master or slave operation ❐ FIFOs can use externally supplied clock or asynchronous strobes ❐ Easy interface to ASIC and DSP ICs ■ Vectored for FIFO and GPIF Interrupts ■ Up to 40 general purpose IOs (GPIO) ■ Four package options: ❐ 128-pin TQFP ❐ 100-pin TQFP ❐ 56-pin SSOP ❐ 56-pin QFN Pb-free Errata: For information on silicon errata, see “Errata” on page 71. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-08039 Rev. L • San Jose, CA 95134-1709 • 408-943-2600 Revised March 9, 2014 1 page CY7C64713 Figure 1. Crystal Configuration C1 24 MHz C2 12 pF 12 pF 20 × PLL 12-pF capacitor values assumes a trace capacitance of 3 pF per side on a four layer FR4 PCA Table 1. Special Function Registers x 8x 9x 0 IOA IOB 1 SP EXIF 2 DPL0 MPAGE 3 DPH0 4 DPL1 5 DPH1 6 DPS 7 PCON 8 TCON SCON0 9 TMOD SBUF0 A TL0 AUTOPTRH1 B TL1 AUTOPTRL1 C TH0 reserved D TH1 AUTOPTRH2 E CKCON AUTOPTRL2 F reserved Ax IOC INT2CLR INT4CLR IE EP2468STAT EP24FIFOFLGS EP68FIFOFLGS AUTOPTRSETUP Bx IOD IOE OEA OEB OEC OED OEE IP EP01STAT GPIFTRIG GPIFSGLDATH GPIFSGLDATLX GPIFSGLDATLNOX Cx SCON1 SBUF1 T2CON RCAP2L RCAP2H TL2 TH2 Dx PSW EICON Ex ACC EIE Fx B EIP I2C Bus FX1 supports the I2C bus as a master only at 100/400 KHz. SCL and SDA pins have open drain outputs and hysteresis inputs. These signals must be pulled up to 3.3 V, even if no I2C device is connected. Buses All packages: 8 or 16-bit ‘FIFO’ bidirectional data bus, multiplexed on I/O ports B and D. 128-pin package: adds 16-bit output only 8051 address bus, 8-bit bidirectional data bus. USB Boot Methods During the power up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0). Alternatively, it boot-loads the EEPROM contents into an internal RAM (0xC2). If no EEPROM is detected, FX1 enumerates using internally stored descriptors. The default ID values for FX1 are VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip revision).[2] Table 2. Default ID Values for FX1 Default VID/PID/DID Vendor ID 0x04B4 Cypress Semiconductor Product ID 0x6473 EZ-USB FX1 Device release 0xAnnn Depends on chip revision (nnn = chip revision where first silicon = 001) Notes 2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly. Document Number: 38-08039 Rev. L Page 5 of 74 5 Page CY7C64713 Figure 5. Register Addresses FFFF F000 EFFF E800 E7FF E7C0 E7BF E780 E77F E740 E73F E700 E6FF E500 E4FF E480 E47F E400 E3FF E200 E1FF E000 4 KBytes EP2-EP8 buffers (8 x 512) Not all Space is available for all transfer types 2 KBytes RESERVED 64 Bytes EP1IN 64 Bytes EP1OUT 64 Bytes EP0 IN/OUT 64 Bytes RESERVED 8051 Addressable Registers (512) Reserved (128) 128 bytes GPIF Waveforms Reserved (512) 512 bytes 8051 xdata RAM Endpoint RAM Size ■ 3 × 64 bytes ■ 8 × 512 bytes (Endpoints 0 and 1) (Endpoints 2, 4, 6, 8) Organization ■ EP0—Bidirectional endpoint zero, 64 byte buffer ■ EP1IN, EP1OUT—64 byte buffers, bulk or interrupt ■ EP2, 4, 6, 8—Eight 512-byte buffers, bulk, interrupt, or isochronous, of which only the transfer size is available. EP4 and EP8 are double buffered, while EP2 and 6 are either double, triple, or quad buffered. Regardless of the physical size of the buffer, each endpoint buffer accommodates only one full speed packet. For bulk endpoints, the maximum number of bytes it can accommodate is 64, even though the physical buffer size is 512 or 1024. For an ISOCHRONOUS endpoint the maximum number of bytes it can accommodate is 1023. For endpoint configuration options, see Figure 6 on page 12. Setup Data Buffer A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup data from a CONTROL transfer. Default Alternate Settings In the following table, ‘0’ means “not implemented”, and ‘2×’ means “double buffered”. Table 6. Default Alternate Settings Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) External FIFO Interface Architecture The FX1 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of these buffers depend on the USB transfer mode as described in the section Organization. In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic. The transfer logic takes two forms: the GPIF for internally generated control signals or the slave FIFO interface for externally controlled transfers. Document Number: 38-08039 Rev. *L Page 11 of 74 11 Page

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