|
|
PDF MCM62995A Data sheet ( Hoja de datos )
| Número de pieza | MCM62995A | |
| Descripción | 16K x 16 Bit Asynchronous/Latched Address Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MCM62995A (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
MCM62995A
16K x 16 Bit Asynchronous/Latched
Address Fast Static RAM
The MCM62995A is a 262,144 bit latched address static random access memory
organized as 16,384 words of 16 bits, fabricated using Motorola's high-performance
silicon-gate CMOS technology. The device integrates a 16K x 16 SRAM core with
advanced peripheral circuitry consisting of address and data input latches, active high
and active low chip enables, separate upper and lower byte write strobes, and a fast
output enable. This device has increased output drive capability supported by multiple
power pins. In addition, the output levels can be either 3.3 V or 5 V TIL compatible by
choice of the appropriate output bus power supply.
Address, data in, and chip enable latches are provided. When latch enable
(LE for address and chip enables and DL for data in) is high, the address,
data in, and chip enable latches are in the transparent state. If latch enable
(LE, DL) is tied high, the device can be used as an asynchronous SRAM.
When latch enable (LE, DL) is low, the address, data in and chip enable
latches are in the latched state. This input latch simplifies read and write
DOB
cycles by guaranteeing address and data-in hold time in a simple fashion.
D09
Dual write strobes (BWL and BWR) are provided to allow individually write- VCCO
able bytes. BWL controls DOO - D07 (the lower bits), while BWH controls
D08 - D015 (the upper bits).
Additional power supply pins have been utilized and placed on the package
for maximum performance. In addition, the output buffer power pins are elec-
trically isolated from the other two and supply power only to the output buffers.
This allows connecting the output buffers to 3.3 V instead of 5.0 V if desired. If
3.3 V output levels are chosen, the output buffer impedance in the "high" state
is approximately equal to the impedance in the "low" state thereby allowing
simplified transmission line terminations.
The MCM62995A is available in a 52 pin plastic leaded chip carrier (PLCC).
VSSO
DOlO
DOll
D012
D013
VSSO
VCCO
D014
D015
NC
This device is ideally suited for systems which require wide data bus widths,
cache memory and tag RAMs. See Figure 2 for applications information.
• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Buffers
• Fast Access Times: 12115/20/25 ns Max
• Byte Writeable via Dual Write Strobes with Abort Write Capability
• Separate Data Input Latch for Simplified Write Cycles
Address and Chip Enable Input Latches
• Common Data Inputs and Data Outputs
• Output Enable Controlled Three-State Outputs
• High Output Drive Capability: 85 pFIOutput at Rated Access Time
• High Board Density 52 Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778
PIN ASSIGNMENT
~ ~ Iwl~l~ J~~I;: ~ ~1C!l ~ W
6 5 4 3 2 1 52 51 50 49 4B 47
46
9
10
11
12
13
14
15
16
17
lB
19 35
20 34
21 22 23 24 25 26 27 2B 29 30 31 32 33
NC
D07
D06
VCCO
VSSO
D05
D04
D03
D02
VSSO
VCCO
DOl
DOO
PIN NAMES
AO-A13 ................ Address Inputs
LE ........................ Latch Enable
DL .................. Data Latch Enable
IN ........................ Write Enable
BWL . . . . . . . . . . . .. Byte Write Strobe Low
BWH ............ Byte Write Strobe High
E ............... Active High Chip Enable
E . . . . . . . . . . . . . .. Active Low Chip Enable
G ...................... Output Enable
DOO - D015 . . . . . . . . .. Data Input/Output
VCC ................ +5 V Power Supply
VCCO ....... Output Buffer Power Supply
VSSO ............ Output Buffer Ground
VSS .......................... Ground
NC ........................ No Connect
All power supply and ground pins must be
connected for proper operation of the device.
VCC ~ VCCO at all times including power up.
MCM62995A
4-130
MOTOROLA FAST SRAM DATA
1 page  
LE
XXXll(LATCH ENABLE)
A(ADDRESS)
E
(CHIP ENABLE)
Q(DATAOUn
ASYNCHRONOUS READ CYCLES
\XxxX)
G
(OUTPUT ENABLE)
W
X!XXY(WRITE ENABLE)
\XXXX)
DL(DATA
LATCH ENABLE)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
BWx(BYTE
WRITE ENABLE)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
MCM62995A
4·134
MOTOROLA FAST SRAM DATA
5 Page 
LE
(LATCH ENABLE)
A(ADDRESS)
LATCHED WRITE CYCLES
E
(CHIP ENABLE)
W
(WRITE ENABLE)
I BWx(BYTE
WRITE ENABLE)
DATA·IN
DL(DATA
LATCH ENABLE)
Q(DATAOUT)
(OUTPUT
G
ENABLE)
\~~/\~--------------
MCM62995A
4-140
MOTOROLA FAST SRAM DATA
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MCM62995A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MCM62995A | 16K x 16 Bit Asynchronous/Latched Address Fast Static RAM | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |