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PDF MR82C84A Data sheet ( Hoja de datos )
| Número de pieza | MR82C84A | |
| Descripción | CMOS Clock Generator Driver | |
| Fabricantes | Intersil | |
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Data Sheet
September 9, 2015
82C84A
FN2974.4
CMOS Clock Generator Driver
The Intersil 82C84A is a high performance CMOS Clock
Generator-driver which is designed to service the requirements
of both CMOS and NMOS microprocessors such as the
80C86, 80C88, 8086 and the 8088. The chip contains a crystal
controlled oscillator, a divide-by-three counter and complete
“Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external
frequency source from DC to 25MHz. Crystal controlled
operation to 25MHz is guaranteed with the use of a parallel,
fundamental mode crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over
temperature and voltage ranges.
Power consumption is a fraction of that of the equivalent
bipolar circuits. This speed-power characteristic of CMOS
permits the designer to custom tailor his system design with
respect to power and/or speed requirements.
Features
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
- M82C84A . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinouts
82C84A
(PDIP, CERDIP)
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
18 VCC
17 X1
16 X2
15 ASYNC
14 EFI
13 F/C
12 OSC
11 RES
10 RESET
82C84A (PLCC, CLCC)
TOP VIEW
RDY1
READY
RDY2
AEN2
NC
4
5
6
7
8
NO
LON3GER2AVAIL1ABL2E0OR1S9UPP11111O54876RTENFEXAD/F2CSCIYNC
9 10 11 12 13
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 1997, 2002, 2005, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
82C84A
Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The
output of the oscillator is buffered and brought out on OSC
so that other system timing signals can be derived from this
stable, crystal-controlled source.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER
TYPICAL CRYSTAL SPEC
Frequency
2.4 - 25MHz, Fundamental, “AT” cut
Type of Operation
Unwanted Modes
Load Capacitance
Parallel
6dB (Minimum)
18 - 32pF
Capacitors C1, C2 are chosen such that their combined
capacitance
CT = C-C----11-----+x-----CC----22-- (Including stray capacitance)
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is
accomplished with two flip-flops. (See Figure 1). The counter
output is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
oscillator or the EFI input as the clock for the 3 counter. If
the EFI input is selected as the clock source, the oscillator
section can be used independently for another clock source.
Output is taken from OSC.
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed to
drive the 80C86, 80C88 processors directly. PCLK is a
peripheral clock signal whose output frequency is 1/2 that of
CLK. PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to
accommodate two system busses. Each input has a qualifier
(AEN1 and AEN2, respectively). The AEN signals validate
their respective RDY signals. If a Multi-Master system is not
being used the AEN pin should be tied LOW.
Synchronization is required for all asynchronous active-going
edges of either RDY input to guarantee that the RDY setup
and hold times are met. Inactive-going edges of RDY in
normally ready systems do not require synchronization but
must satisfy RDY setup and hold as a matter of proper system
design.
The ASYNC input defines two modes of READY
synchronization operation.
When ASYNC is LOW, two stages of synchronization are
provided for active READY input signals. Positive-going
asynchronous READY inputs will first be synchronized to flip-
flop one of the rising edge of CLK (requiring a setup time
tR1VCH) and the synchronized to flip-flop two at the next
falling edge of CLK, after which time the READY output will go
active (HIGH). Negative-going asynchronous READY inputs
will be synchronized directly to flip-flop two at the falling edge
of CLK, after which the READY output will go inactive. This
mode of operation is intended for use by asynchronous
(normally not ready) devices in the system which cannot be
guaranteed by design to meet the required RDY setup timing,
TR1VCL, on each bus cycle.
When ASYNC is high or left open, the first READY flip-flop is
bypassed in the READY synchronization logic. READY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchronous devices that can be guaranteed to
meet the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
5 FN2974.4
September 9, 2015
5 Page 
Burn-In Circuits
F9
VCC
GND
F6
F5
VCC
GND
F7
F8
VCC
GND
R2
R2
R2
R2
R2
R2
82C84A
MD82C84A CERDIP
VCC
C1
R1
1
2
R1
3
R1
4
5
R1
6
R1
7
8
9
18
17
16
R3
15
R1
14
R1
13
12
R1
11
10
R1
R2 F0
OPEN
F10
F1
R2 F11
R2 VCC
GND
R2
R2
F12
VCC
GND
MR82C84A CLCC
VCC
C1
F5
VCC / 2
F7
F8
OPEN
R4
R4
R4
R4
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
OPEN
R4 F10
R4 F1
R4 F11
OPEN
NOTES:
VCC = 5.5V 0.5V, GND = 0V.
VIH = 4.5V 10%.
VIL = -0.2 to 0.4V.
R1 = 47k, 5%.
R2 = 10k, 5%.
R3 = 2.2k, 5%.
R4 = 1.2k, 5%.
C1 = 0.01F (minimum).
F0 = 100kHz 10%.
F1 = F0/2, F2 = F1/2, . . . F12 = F11/2.
11
FN2974.4
September 9, 2015
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MR82C84A.PDF ] | |
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