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PDF MC100LVEL33 Data sheet ( Hoja de datos )
| Número de pieza | MC100LVEL33 | |
| Descripción | Divider | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC100LVEL33 (archivo pdf) en la parte inferior de esta página. Total 3 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
÷4 Divider
The MC100LVEL33 is an integrated ÷4 divider. The differential clock
inputs and the VBB allow a differential, single-ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a 0.01µF capacitor. Also note that the VBB is designed to be
used as an input bias on the EL33 only, the VBB output has limited current
sink and source capability. The LVEL is functionally equivalent to the
EL33 and works from a low voltage supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the reset
allows for the synchronization of multiple LVEL33’s in a system.
• 630ps Propagation Delay
• 4.0GHz Toggle Frequency
• High Bandwidth Output Transitions
• Operates from –3.3V (or 3.3V) Supply
• 75kΩ Internal Input Pulldown Resistors
• >2000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Reset 1
CLK 2
CLK 3
8 VCC
R
7Q
÷4
6Q
VBB 4
5 VEE
MC100LVEL33
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
PIN DESCRIPTION
PIN
CLK
Reset
VBB
Q
FUNCTION
Clock Inputs
Asynch Reset
Ref Voltage Output
Data Ouputs
8/96
© Motorola, Inc. 1996
3–1
REV 0
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet MC100LVEL33.PDF ] | |
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