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PDF MC10E136 Data sheet ( Hoja de datos )
| Número de pieza | MC10E136 | |
| Descripción | 6-BIT UNIVERSAL UP/DOWN COUNTER | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC10E136 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
6ĆBit Universal Up/Down Counter
MC10E136
The MC10E/100E136 is a 6-bit synchronous, presettable, cascadable
universal counter. The device generates a look-ahead-carry output and
accepts a look-ahead-carry input. These two features allow for the
cacading of multiple E136’s for wider bit width counters that operate at
very nearly the same frequency as the stand alone counter.
• 550 MHz Count Frequency
• Fully Synchronous Up and Down Counting
• Internal 75 kΩ Input Pulldown Resistors
• Look-Ahead-Carry Input and Output
• Asynchronous Master Reset
• Extended 100E VEE Range of –4.2 V to –5.46 V
MC100E136
6-BIT UNIVERSAL
UP/DOWN COUNTER
The CLOUT output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT output will pulse
LOW for one clock cycle when the counter reaches terminal count. For
more information on utilizing the look-ahead-carry features of the device
please refer to the applications section of this data sheet. The differential
COUT output facilitates the E136’s use in programmable divider and
self-stopping counter applications.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Unlike the H136 and other similar universal counter designs the E136
carry out and look-ahead-carry out signals are registered on chip. This
design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet carefully. Note specifically (see logic diagram) the operation of the carry out
outputs and the look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input pulldown resistor. The master reset is an asynchronous
signal which when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136 to function properly, in fact if these outputs will not be used in a system it is
recommended to save power and minimize noise that they be left open. This practice will minimize switching noise which can
reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system.
PIN NAMES
Pin
D0 – D5
Q0 – Q5
S1, S2
MR
CLK
COUT, COUT
CLOUT
CIN
CLIN
Function
Preset Data Inputs
Data Inputs
Mode Control Pins
Master Reset
Clock Input
Carry-Out Output (Active LOW)
Look-Ahead-Carry Out (Active LOW)
Carry-In Input (Active LOW)
Look-Ahead-Carry In Input (Active LOW)
D3 D4 D5 VCCO Q5 Q4 VCCO
25 24 23 22 21 20 19
D2 26
18 Q3
S2 27
17 Q2
S1 28
VEE 1
Pinout: 28-lead PLCC
(Top View)
16 VCC
15 VCCO
CLK 2
14 COUT
FUNCTION TABLE (Expanded truth table on page 2–4)
S1 S2 CIN MR CLK
Function
LLXL
LHL L
L HH L
HL L L
HLHL
HHX L
XXXH
Z Preset Parallel Data
Z Increment (Count Up)
Z Hold Count
Z Decrement (Count Down)
Z Hold Count
Z Hold Count
X Reset (Qn = LOW)
CIN 3
13 COUT
CLIN 4
12 CLOUT
56
7 8 9 10 11
MR D1 D0 VCCO Q0 Q1 VCCO
* All VCC and VCCO pins are tied together on the die.
5/95
© Motorola, Inc. 1996
2–1
REV 2
1 page  
MC10E136 MC100E136
APPLICATIONS INFORMATION
Overview
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. Using the S1 and S2 control
pins the user can select between preset, count up, count
down and hold count. The master reset pin will reset the
internal counter, and set the COUT, CLOUT, and CLIN
flip-flops. Unlike previous 136 type counters the carry out
outputs will go to a high state during the preset operation. In
addition since the carry out outputs are registered they will
not go low if terminal count is loaded into the register. The
look-ahead-carry out output functions similarly.
Note from the schematic the use of the master information
from the least significant bits for control of the two carry out
functions. This architecture not only reduces the carry out
delay, but is essential to incorporate the registered carry out
functions. In addition to being faster, because these functions
are registered the resulting carry out signals are stable and
glitch free.
Cascading Multiple E136 Devices
Many applications require counters significantly larger
than the 6 bits available with the E136. For these applications
several E136 devices can be cascaded to increase the bit
width of the counter to meet the needs of the application.
In the past cascading several 136 type universal counters
necessarily impacted the maximum count frequency of the
resulting counter chain. This performance impact was the
result of the terminal count signal of the lower order counters
having to ripple through the entire counter chain. As a result
past counters of this type were not widely used in large bit
counter applications.
An alternative counter architecture similar to the E016
binary counter was implemented to alleviate the need to
ripple propagate the terminal count signal. Unfortunately
these types of counters require external gating for cascading
designs of more than two devices. In addition to requiring
additional components, these external gates limit the
cascaded count frequency to a value less than the free
running count frequency of a single counter. Although there is
a performance impact with this type of architecture it is minor
compared to the impact of the ripple propagate designs. As a
result the E016 type counters have been used extensively in
applications requiring very high speed, wide bit width
synchronous counters.
Motorola has incorporated several improvements to past
universal counter designs in the E136 universal counter.
These enhancements make the E136 the unparalleled leader
in its class. With the addition of look-ahead-carry features on
the terminal count signal, very large counter chains can be
designed which function at very nearly the same clock
frequency as a single free running device. More importantly
these counter chains require no external gating. Figure 1
below illustrates the interconnect scheme for using the
look-ahead-carry features of the E136 counter.
Q0 –> Q5
Q0 –> Q5
CLOCK
“LO”
“LO”
CLK
LSB
CIN COUT “LO”
CLIN CLOUT
CLK
CIN COUT
CLIN CLOUT
D0 –> D5
D0 –> D5
Q0 –> Q5
CLK
CIN COUT
CLIN CLOUT
D0 –> D5
CLK
CLOUT
111101
COUT
111110
111111
000000
Figure 1. 24-bit Cascaded E136 Counter
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–5
Q0 –> Q5
CLK
MSB
CIN COUT
CLIN CLOUT
D0 –> D5
000001
MOTOROLA
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC10E136.PDF ] | |
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