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PDF MB85R4001A Data sheet ( Hoja de datos )
| Número de pieza | MB85R4001A | |
| Descripción | Memory FRAM | |
| Fabricantes | Fujitsu | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
Memory FRAM
4 M Bit (512 K × 8)
MB85R4001A
DS501-00005-5v1-E
■ DESCRIPTIONS
The MB85R4001A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 524,288
words × 8 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS
process technologies.
The MB85R4001A is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R4001A can be used for 1010 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
The MB85R4001A uses a pseudo-SRAM interface.
■ FEATURES
• Bit configuration
: 524,288 words × 8 bits
• Read/write endurance
: 1010 times / byte
• Data retention
: 10 years ( + 55 °C), 55 years ( + 35 °C)
• Operating power supply voltage
: 3.0 V to 3.6 V
• Low power operation
: Operating power supply current 15 mA (Typ)
Standby current 50 μA (Typ)
• Operation ambient temperature range : − 40 °C to + 85 °C
• Package
: 48-pin plastic TSOP (FPT-48P-M48)
RoHS compliant
Copyright 2011-2015 FUJITSU SEMICONDUCTOR LIMITED
2015.5
1 page  
MB85R4001A
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
Condition
(within recommended operating conditions)
Value
Unit
Min Typ Max
Input Leakage Current*1
|ILI| VIN = 0 V to VDD
⎯ ⎯ 10 μA
Output Leakage Current
|ILO|
VOUT = 0 V to VDD,
CE1 = VIH or OE = VIH
⎯ ⎯ 10 μA
Operating Power Supply
Current*2
IDD
CE1 = 0.2 V, CE2 = VDD−0.2 V,
Iout = 0 mA
⎯
15
20 mA
CE1 ≥ VDD−0.2 V
Standby Current*3
ISB CE2 ≤ 0.2 V
⎯ 50 150 μA
OE ≥ VDD−0.2 V, WE ≥ VDD−0.2 V
High Level Input Voltage
VIH VDD = 3.0 V to 3.6 V
VDD × 0.8
⎯
VDD + 0.5(
≤ 4.0)
V
Low Level Input Voltage
VIL VDD = 3.0 V to 3.6 V
− 0.5 ⎯
+ 0.6 V
High Level Output Voltage VOH IOH = −1.0 mA
VDD × 0.8 ⎯ ⎯ V
Low Level Output Voltage VOL IOL = 2.0 mA
⎯ ⎯ 0.4 V
*1 : This also applies to DNU pins.
*2 : During the measurement of IDD, the Address and Data In were taken to only change once per active cycle.
Iout: output current
*3 : All pins other than setting pins shall be input at the CMOS level voltages such as H ≥ VDD − 0.2 V, L ≤ 0.2 V.
DS501-00005-5v1-E
5
5 Page 
MB85R4001A
■ POWER ON/OFF SEQUENCE
tPD
tR tPU
VDD
CE2
3.0 V
VIH (Min)
VDD
CE2
3.0 V
VIH (Min)
1.0 V
VIL (Max)
0V
CE2 ≤ 0.2 V
CE1 > VDD × 0.8*
CE1 : Don't Care
CE1 > VDD × 0.8*
1.0 V
VIL (Max)
0V
CE1
* : CE1 (Max) < VDD + 0.5 V
CE1
Parameter
CE1 level hold time for Power OFF
CE1 level hold time for Power ON
Power supply rising time
Symbol
tPD
tPU
tR
Min
85
85
0.05
Value
Typ
⎯
⎯
⎯
Max
⎯
⎯
200
Unit
ns
ns
ms
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
In case the power is turned on or off, use the power supply reset IC and fix the CE2 to low level, to prevent
unexpected writing. Use either of CE1 or CE2, or both to disable control of the device.
■ FRAM CHARACTERISTICS
Item
Min Max
Unit
Parameter
Read/Write Endurance*1 1010
⎯ Times/byte Operation Ambient Temperature TA = + 85 °C
Data Retention*2
10 ⎯
Operation Ambient Temperature TA = + 55 °C
Years
55 ⎯
Operation Ambient Temperature TA = + 35 °C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2 : Minimum values define retention time of the first reading/writing data right after shipment, and these values
are calculated by qualification results.
■ NOTES ON USE
We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
DS501-00005-5v1-E
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MB85R4001A.PDF ] | |
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