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PDF MD56V62160E Data sheet ( Hoja de datos )
| Número de pieza | MD56V62160E | |
| Descripción | SYNCHRONOUS DYNAMIC RAM | |
| Fabricantes | LAPIS | |
| Logotipo |  |
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MD56V62160E
4-Bank 1,048,576-Word 16-Bit SYNCHRONOUS DYNAMIC RAM
FEDD56V62160E-07
Issue Date: Nov. 18, 2013
DESCRIPTION
The MD56V62160E is a 4-Bank 1,048,576-word 16-bit Synchronous dynamic RAM fabricated in
LAPIS Semiconductor’s silicon-gate CMOS technology. The device operates at 3.3 V. The inputs and
outputs are LVTTL compatible.
FEATURES
• Silicon gate, quadruple poly-silicon CMOS, 1-transistor memory cell
• 4-Bank 1,048,576-word 16-bit configuration
• Single 3.3 V power supply, 0.3 V tolerances
• Input : LVTTL compatible
• Output : LVTTL compatible
• Refresh : 4096 cycles/64 ms
• Programmable data transfer mode
- CAS Latency (2, 3)
- Burst Length (1, 2, 4, 8, Full Page)
- Data scramble (sequential, interleave)
• CBR auto-refresh, Self-refresh capability
• Packages:
54-pin 400 mil plastic TSOP (TypeII) (P-TSOP(2)54-400-0.80-UK6)
(Product: MD56V62160E-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Family
MD56V62160E-10
Max.
Frequency
100 MHz
Access Time (Max.)
tAC2
6 ns
tAC3
6 ns
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1 page  
FEDD56V62160E-07
MD56V62160E
DC Characteristics
Parameter Symbol
Condition
MD56V62160
E-10
Bank
CKE Others
Min.
Max.
Output High
Voltage
VOH
IOH =
2.0mA
2.4
Output Low
Voltage
VOL
IOL =
2.0mA
0.4
Input Leakage
Current
ILI
10
10
Output Leakage
Current
ILO
10
10
Average Power
Supply Current
(Operating)
Power Supply
Current
(Standby)
ICC1
One Bank
Active
tCC = Min.
CKE VIH tRC = Min.
No Burst
Both
ICC1D Banks
Active
tCC = Min.
CKE VIH
tRC = Min.
tRRD = Min.
No Burst
Both
ICC2 Banks
CKE VIH tCC = Min.
Precharge
70
115
30
Average Power
Supply Current
(Clock
Suspension)
Both
ICC3S Banks
Active
CKE VIL tCC = Min.
3
Average Power
Supply Current
(Active Standby)
ICC3
One Bank
Active
CKE VIH tCC = Min.
30
Power Supply
Current (Burst)
Both
ICC4 Banks
Active
CKE VIH tCC = Min.
90
Power Supply
Current
(Auto-Refresh)
ICC5
One Bank
Active
CKE VIH
tCC = Min.
tRC = Min.
115
Average Power
Supply Current
(Self-Refresh)
Both
ICC6 Banks
CKE VIL tCC = Min.
Precharge
2
Average Power
Supply Current
(Power Down)
Both
ICC7 Banks
CKE VIL tCC = Min.
Precharge
2
Notes: 1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycles. DC
Unit Note
V
V
A
A
mA 1,2
mA 1,2
mA 3
mA 2
mA 3
mA 1,2
mA 2
mA
mA
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5 Page 
FEDD56V62160E-07
MD56V62160E
*Notes: 1. When CS is set “High” at a clock transition from “Low” to “High”, all inputs except CLK, CKE,
UDQM and LDQM are invalid.
2. When issuing an active, read or write command, the bank is selected by A12 and A13.
A11 A12
00
01
10
11
Active, read or write
Bank A
Bank B
Bank C
Bank D
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A10 A12 A13
Operation
0 0 0 After the end of burst, bank A holds the idle status.
1 0 0 After the end of burst, bank A is precharged automatically.
0 0 1 After the end of burst, bank B holds the idle status.
1 0 1 After the end of burst, bank B is precharged automatically.
0 1 0 After the end of burst, bank C holds the idle status.
1 1 0 After the end of burst, bank C is precharged automatically.
0 1 1 After the end of burst, bank D holds the idle status.
1 1 1 After the end of burst, bank D is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs.
A10 A12 A13
Operation
0 0 0 Bank A is precharged.
0 0 1 Bank B is precharged.
0 1 0 Bank C is precharged.
0 1 1 Bank D is precharged.
1 X X All banks are precharged.
5. The input data and the write command are latched by the same clock (Write latency = 0).
6. The output is forced to high impedance by (1CLK+ tOHZ ) after UDQM, LDQM entry.
11/33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MD56V62160E.PDF ] | |
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