PDF IS66WV51216BLL Data sheet ( Hoja de datos )

Número de pieza	IS66WV51216BLL
Descripción	ULTRA LOW POWER PSEUDO CMOS STATIC RAM
Fabricantes	ISSI
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No Preview Available ! IS66WV51216ALL IS66WV51216BLL 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM JANUARY 2010 FEATURES • High-speed access time: 55ns • CMOS low power operation – mW (typical) operating – µW (typical) CMOS standby • Single power supply – 1.7V--1.95V Vdd (66WV51216ALL) (70ns) – 2.5V--3.6V Vdd (66WV51216BLL) (55ns) • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Lead-free available FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS66WV51216ALL/BLL is a high-speed, 8M bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected) or when CS1 is low, CS2 is high and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS66WV51216ALL/BLL is packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). The device is aslo available for die sales. A0-A18 DECODER 512K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CS2 CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 1 1 page IS66WV51216ALL IS66WV51216BLL CAPACITANCE(1) Symbol Parameter Conditions Max. Cin Input Capacitance Vin = 0V 8 Cout Input/Output Capacitance Vout = 0V 10 Note: 1. Tested initially and after any design or process changes that may affect these parameters. Unit pF pF AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 1.7V-1.95V (Unit) 0.4V to Vdd-0.2 5 ns Vref See Figures 1 and 2 2.5V-3.6V (Unit) 0.4V to Vdd-0.3V 5ns Vref See Figures 1 and 2 R1(Ω) R2(Ω) Vref Vtm 1.7V - 1.95V 3070 3150 0.9V 1.8V 2.5V - 3.6V 1029 1728 1.4V 2.8V AC TEST LOADS VTM R1 OUTPUT 30 pF Including jig and scope Figure 1 R2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 VTM R1 OUTPUT 5 pF Including jig and scope Figure 2 R2 5 5 Page IS66WV51216ALL IS66WV51216BLL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) ADDRESS tWC OE CS1 CS2 WE tSCS1 tSCS2 tAW t PWE tHA LB, UB DOUT DIN tSA tHZWE DATA UNDEFINED HIGH-Z tLZWE tSD tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) ADDRESS tWC OE CS1 CS2 WE tSCS1 tSCS2 tAW t PWE tHA LB, UB DOUT DIN tSA tHZWE DATA UNDEFINED HIGH-Z tLZWE tSD tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 11 11 Page

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Número de pieza	Descripción	Fabricantes
IS66WV51216BLL	ULTRA LOW POWER PSEUDO CMOS STATIC RAM	ISSI

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