PDF K4H641638N Data sheet ( Hoja de datos )

Número de pieza	K4H641638N
Descripción	64Mb N-die DDR SDRAM
Fabricantes	Samsung
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No Preview Available ! K4H641638N DDR SDRAM 64Mb N-die DDR SDRAM Specification 66 TSOP-II & 60 FBGA with Lead-Free and Halogen-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 30 Rev. 1.4 August 2009 1 page K4H641638N 4.0 Pin / Ball Description 66pin TSOP - II 16Mb x 16 DDR SDRAM VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 66Pin TSOPII 57 11 (400mil x 875mil) 56 12 (0.65mm Pin Pitch) 55 13 54 14 15 Bank Address BA0~BA1 16 53 52 51 17 18 19 Auto Precharge A10 50 49 48 20 47 21 46 22 45 23 44 24 43 25 42 26 41 27 40 28 39 29 38 30 37 31 36 32 35 33 34 64Mb TSOP-II Package Pinout VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS Organization 4Mx16 Row Address A0~A11 Column Address A0-A7 DM is internally loaded to match DQ and DQS identically. Row & Column address configuration 5 of 30 Rev. 1.4 August 2009 5 Page K4H641638N DDR SDRAM 8.0 Command Truth Table (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9, A11 ~ A12 Note Register Extended MRS H XLL L L OP CODE 1, 2 Register Mode Register Set H XLL L L OP CODE 1, 2 Auto Refresh H 3 H LL L H X Entry L 3 Refresh Self Refresh LH H H Exit L H X 3 HX X X 3 Bank Active & Row Addr. H XLL HH V Row Address Read & Auto Precharge Disable Column Address Auto Precharge Enable H X LH L H V L H Column Address 4 4 Write & Auto Precharge Disable Column Address Auto Precharge Enable H X LH L L V L H Column Address 4 4, 6 Burst Stop H X LH H L X 7 Precharge Bank Selection All Banks V H XLL H L X L H X 5 Active Power Down Entry HX X X HL LV V V X Exit L H X X X X Precharge Power Down Mode Entry Exit HX X X HL LH H H HX X X LH LV V V X DM(UDM/LDM for x16 only) H X X8 HX X X 9 No operation (NOP) : Not defined HX X LH H H 9 Note : 1. OP Code : Operand Code. A0 ~ A12& BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. 11 of 30 Rev. 1.4 August 2009 11 Page

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