PE43503 Datasheet PDF - Peregrine Semiconductor
| Part Number | PE43503 | |
| Description | RF Digital Attenuator | |
| Manufacturers | Peregrine Semiconductor | |
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Product Description
The PE43503 is a HaRP™-enhanced, high linearity, 5-bit RF
Digital Step Attenuator (DSA) covering a 31 dB attenuation
range in 1 dB steps. The Peregrine 50Ω RF DSA provides a
serial CMOS control interface. It maintains high attenuation
accuracy over frequency and temperature and exhibits very low
insertion loss and low power consumption. Performance does
not change with Vdd due to on-board regulator. This next
generation Peregrine DSA is available in a 4x4 mm 24-lead
QFN footprint.
The PE43503 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Package Type
24-lead 4x4x0.85 mm QFN Package
Product Specification
PE43503
50 Ω RF Digital Attenuator
5-bit, 31 dB, 9 kHz - 6.0 GHz
Features
• HaRP™-enhanced UltraCMOS™ device
• Attenuation: 1 dB steps to 31 dB
• High Linearity: Typical +58 dBm IP3
• Excellent low-frequency performance
• 3.3 V or 5.0 V Power Supply Voltage
• Fast switch settling time
• Programming Modes:
• Direct Parallel
• Latched Parallel
• Serial
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
• No DC blocking capacitors required
• Packaged in a 24-lead 4x4x0.85 mm QFN
Figure 2. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
Parallel Control 5
Serial In
CLK
LE
Control Logic Interface
A0 A1
Document No. 70-0252-05 │ www.psemi.com
A2
P/S
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
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PE43503
Product Specification
Table 5. Control Voltage
State
Bias Condition
Low 0 to +1.0 Vdc at 2 µA (typ)
High
+2.6 to +5 Vdc at 10 µA (typ)
Table 6. Latch and Clock Specifications
Latch Enable
X
↑
Shift Clock
↑
X
Function
Shift Register Clocked
Contents of shift register
transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting
Attenuation Setting
D6 D5 D4 D3 D2
RF1-RF2
LLLLL
LLL LH
LLLHL
Reference I.L.
1 dB
2 dB
L LH L L
4 dB
LHL L L
HLL LL
HHHHH
8 dB
16 dB
31 dB
Table 8. Attenuation Word Truth Table
Attenuation Word
Attenuation
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
Setting
RF1-RF2
LL L L L L L
L Reference I.L.
LLLL LHL
L
1 dB
LL L L HL L
L
2 dB
LLLHLLL
L
4 dB
LLHL LLL
L
8 dB
LHL L L L L
L
16 dB
LHHHHHL
L
31 dB
Table 9. Serial Register Map
MSB (last in)
LSB (first in)
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
Attenuation Word
Bits must be set to logic low
Attenuation Word is derived directly from the attenuation value. For example, to program the 13 dB state:
Attenuation Word: Multiply by 4 and convert to binary → 4 *13 dB → 52 → 00110100
Serial Input: 00110100
Document No. 70-0252-05 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for PE43503 electronic component. |
| Information | Total 11 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ PE43503.PDF Datasheet ] | |
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