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PDF L98SI Data sheet ( Hoja de datos )
| Número de pieza | L98SI | |
| Descripción | OCTAL SERIAL SOLENOID DRIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L98SI
OCTAL SERIAL SOLENOID DRIVER
. EIGHT LOW RDSon DMOS OUTPUTS
(0.5Ω AT IO = 1A @ 25°C VCC = 5V± 5%)
. 8 BIT SERIAL INPUT DATA (SPI)
. 8 BIT SERIAL DIAGNOSTIC OUTPUT FOR
OVERLOADAND OPENCIRCUIT CONDITIONS
. OUTPUT SHORT CIRCUIT PROTECTION
. CHIPENABLESELECTFUNCTION (active low)
. INTERNAL 36V CLAMPING FOR EACH OUT-
PUT
. CASCADABLE WITH ANOTHER OCTAL
DRIVER
. LOW QUIESCENT CURRENT (10mA MAX.)
. PACKAGE PowerSO20
DESCRIPTION
The L98SI is an octal low side solenoiddriver rea
lized in Multipower-BCD technologyparticularlysui-
ted for driving lamps, relays and solenoids in indu-
MULTIPOWER BCD TECHNOLOGY
PowerSO20
ORDERING NUMBER: L98SI
strial environment. The L98SI DMOS outputshave
very low power consumption.
Data is transmitted serially to the device using the
Serial Peripheral Interface (SPI) protocol.
The L98SI features the outputs status monitoring
function.
BLOCK DIAGRAM
April 1998
1/9
1 page  
L98SI
FUNCTIONAL DESCRIPTION
TheL98SIDMOS outputisa lowoperatingpowerde-
vice featu-ring, eight 1Ω RDSON DMOS drivers with
transient protection circuits in output stages. Each
channel is independently controlled by an output
latch and a common RESET line which disables all
eightoutputs.Thedriverhaslow saturationandshort
circuit protectionand can drive inductive and resistive
loads such as solenoids, lamps and relais. Data is
transmitted to the device serially using the Serial Pe-
ripheral Interface(SPI) protocol. The circuit receives
8 bitserial databy meansof the serialinput(SI)which
is stored in an internal register to control the output
drivers. The serial output (SO) provides 8 bit of dia-
gnosticdatarepresentingthe voltagelevel at the dri-
ver output. This allows the microprocessor to
diagnose the condition of the output drivers.
The output saturation voltage is monitored by a
comparator for an out of saturation condition and is
able to unlatch the particular driver through the fault
reset line. This circuit is also cascadable with ano-
ther octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
line is low.
Additionally the (SO) is placed in a tri-state mode
when the device is deselected. The negative edge
of the (CE) transfers the voltage level of the drivers
to the shift registerand the positive edge of the (CE)
latchesthe new datafrom the shift registerto the dri-
vers. When CE is Low, data bit contained into the
shift register is transferred to SO output at every
SCLK positive transition while data bit present at SI
input is latched into the shift register on every SCLK
negative transition.
Internal Blocks Description
The internal architecture of the device is based on
the three internal major blocks : the octal shift regi-
ster for talking to the SPI bus, the octal latch for hol-
ding control bits written into the device and the octal
load driver array.
Shift Register
The shift register has both serial and parallel inputs
and serial and parallel outputs. The serial input ac-
cepts data from the SPI bus and the serial output si-
multaneously sends data into the SPI bus. The
parallel outputs are latched into the parallel latch in-
side the L98SI at the end of a datatransfer. The pa-
rallel inputsjam diagnosticdatainto the shift register
at the beginning of a data transfer cycle.
Parallel Latch
The parallel latch holds the input data from the shift
register. This data then actuates the output stages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
output stages. The entire latch may also be cleared
by the RESET signal.
Output Stages
The output stagesprovide an active low drive signal
suitable for 0.75A continuous loads. Each output
has a current limit circuit which limits the maximum
output current to at least 1.05A to allow for high in-
rush currents. Additionally,the outputshaveinternal
zeners set to 36 volts to clamp inductive transients
at turn-off. Each output also has a voltage compa-
rator observing the outputnode. If the voltage exce-
eds 1.8V on an ON output pin, a fault condition is
assumed and the latch driving this particular stage
is reset, turning the output OFF to protect it. The ti-
ming of this action is described below. These com-
parators also provide diagnostic feedback data to
the shift register. Additionally, the comparatorscon-
tainan internalpulldowncurrentwhich will causethe
cell to indicate a low output voltage if the output is
programmedOFF and the output pin is open circui-
ted.
TIMING DATA TRANSFER
Figure #2 shows the overall timing diagram from a
byte transfer to and from the L98SI using the SPI
bus.
CE High to Low Transition
The action begins when the Chip Enable(CE) pin is
pulledlow. The tri-state Serial Output(SO)pin driver
will be enabledentire time that CE is low. At the fal-
ling edge of the CE pin, the diagnostic data from the
voltage comparatorsin the output stages will be lat-
ched into the shift register. If a particular output is
high, a logic one will be jammed into that bit in the
shift register. If the output is low, a logic zero will be
loadedthere. The most significant bit (07) shouldbe
presented at the Serial Input (SI) pin. A zero at this
pin will program an output ON, while a one will pro-
gram the output OFF.
SCLK Transitions
The Serial Clock (SCLK) pin should then be pulled
high. At thispoint the diagnostic bit from the most si-
gnificantoutput(07) will appearat the SO pin.A high
here indicates that the 07 pin is higher than 1.8V.
The SCLK pin shouldthen be toggledlow then high.
New SO data will appearfollowingevery rising edge
of SCLK and new SI data will be latched into the
L98SIshift registeronthe fallingedges.An unlimited
amount of data may be shifted through the device
5/9
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| PDF Descargar | [ Datasheet L98SI.PDF ] | |
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