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PDF L9826 Data sheet ( Hoja de datos )
| Número de pieza | L9826 | |
| Descripción | Octal Low-Side Driver for resistive and inductive loads with serial/parallel input control/ output protection and diagnostic | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L9826
Octal Low-Side Driver for resistive and inductive loads with
serial/parallel input control, output protection and diagnostic
s OUTPUTS CURRENT CAPABILITY UP TO
500mA, RON = 2.2Ω AT TJ = 25°C
s PARALLEL CONTROL INPUTS FOR
OUTPUTS 1 AND 2
s SPI CONTROL FOR OUTPUTS 1 TO 8
s RESET FUNCTION WITH RESET SIGNAL AT
NRES PIN OR UNDERVOLTAGE AT VCC
s - INTRINSIC OUTPUT VOLTAGE CLAMPING
AT TYP. 50V
s OVERCURRENT SHUTDOWN AT OUTPUTS
3 TO 8
s SHORT CIRCUIT CURRENT LIMITATION
AND SELECTIVE THERMAL SHUTDOWN AT
OUTPUTS 1 AND 2
s OUTPUT STATUS DATA AVAILABLE ON THE SPI
SO20 (16+2+2)
ORDERING NUMBER: L9826
DESCRIPTION
The L9826 is a Octal Low-Side Driver Circuit, dedicated
for automotive applications. Output voltage clamping is
provided for flyback current recirculation, when induc-
tive loads are driven. Chip Select and Serial Peripheral
Interface for outputs control and diagnostic data trans-
fer. Parallel Control inputs for two outputs.
BLOCK DIAGRAM
VCC
NON1
NON2
NCS
CLK
SDI
SDO
nRES
VCC
Q1
Diag1
13
2
S Latch / Driver
Fault Latch
R
Overtemperature Detection
VCC
Q2
Diag2
IOL
+
- VDG
CH1
CH2
VCC
VCC
VCC
VCC
Q1
Q2
Q3 Q3
Q4
Q5
Q6
Q7
Q8
Diag1 Diag3
Diag2
Diag3
Diag4 Q4
Diag5 Diag4
Diag6
Diag7
Diag8 Q5
Diag5
Q6
Diag6
Reset
VCC
Undervoltage
RESET
Reset Q7
Diag7
Q8
Diag8
S
Latch / Driver
R
IOL
+
- VDG CH3
CH4
CH5
CH6
CH7
CH8
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
October 2002
GND
1/12
1 page  
L9826
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
Outputs short circuit protection
ISBC Overcurrent shutoff threshold OUT3 ... OUT8
0.45
1.1 A
ILIM
tSCB
Short circuit current limitation
Delay shutdown
OUT1; OUT2
for output 3 ... 8; IOUT ≤ 1/2 ISCB
0.5 1,0 A
0.2 3,0 12
µs
Diagnostics
VDG Diagnostic threshold voltage
0.32·V
CC
0.4·VC
C
V
IOL Open load detection sink
current
Vout = VDG
20 100 µA
tdf Diagnostic detection filter time
for output 1 & 2 on each
diagnostic condition
15 50 µs
Outputs timing
tdon1
Turn ON delay of OUT 1 and 2
NON1, 2 = 50% to VOUT = 0,9·Vbat
NCS = 50% to VOUT = 0,9·Vbat
5 µs
tdon2 Turn ON delay of OUT 3 to 8
NCS = 50% to VOUT = 0,9·Vbat
10 µs
tdoff Turn OFF delay of OUT 1 to 8 NCS = 50% to VOUT = 0,1·Vbat
NON1, 2 = 50% to VOUT = 0,1·Vbat
10 µs
dUon1/dt Turn ON voltage slew-rate
For output 3 to 8; 90% to 30% of
Vbat; RL = 500Ω; Vbat = 16V
0.7
3.5 V/µs
dUon2/dt Turn ON voltage slew-rate
For output 1 and 2; 90% to 30% of
Vbat; RL = 500Ω; Vbat = 16V
2
10 V/µs
dUoff1/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 90% of
Vbat; RL = 500Ω; Vbat = 16V
2
10 V/µs
dUoff2/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 80% of
Vbat; RL = 500Ω; Vbat = 0.9 · Vclp
2
15 V/µs
Serial diagnostic link (Load capacitor at SDO = 100pF)
fclk Clock frequency
50% duty cycle
3 MHz
tclh Minimum time CLK = HIGH
160 ns
tcll Minimum time CLK = LOW
160 ns
tpcld Propagation delay
CLK to data at SDO valid
4,9V ≤ VCC ≤ 5,1V
100 ns
tcsdv
NCS = LOW to data at SDO
active
100 ns
tsclch CLK low before NCS low
Setup time CLK to NCS change H/L 100
ns
5/12
5 Page 
DIM.
MIN.
mm
TYP. MAX. MIN.
inch
TYP. MAX.
A 2.35
2.65 0.093
0.104
A1 0.1
0.3 0.004
0.012
B 0.33
0.51 0.013
0.020
C 0.23
0.32 0.009
0.013
D 12.6
13 0.496
0.512
E 7.4
7.6 0.291
0.299
e 1.27
0.050
H 10
10.65 0.394
0.419
h 0.25
0.75 0.010
0.030
L 0.4
1.27 0.016
0.050
K 0˚ (min.)8˚ (max.)
L9826
OUTLINE AND
MECHANICAL DATA
SO20
B
20
1
e
D
L
A
K
h x 45˚
A1
H
C
11
10
E
SO20MEC
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet L9826.PDF ] | |
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