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PDF RNA52A10T Data sheet ( Hoja de datos )
| Número de pieza | RNA52A10T | |
| Descripción | Dual CMOS system-RESET IC | |
| Fabricantes | Renesas | |
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Data Sheet
RNA52A10T
Dual CMOS system–RESET IC
R03DS0078EJ0200
Rev.2.00
Dec 19, 2015
Description
The RNA52A10T incorporates two reset circuits, one with and one without a delay function, allowing the generation of
separate reset signals for a microprocessor and associated system circuits. The detection voltage of each reset circuit is
determined by the value of an external resistor, and the internal reference voltage is 1.0 V. The CMOS process for the
RNA52A10T means that the device draws only 1.1 μA (typ.). The reset cancellation delay time is set with a high
degree of accuracy by the values of a capacitor and resistor connected with the CD pin. The MR (manual reset) input
pin is provided for the reset circuit with the delay function, and the reset signal is output in response to a high level on
the MR input pin. The MR pin is pulled down by a 2-MΩ internal resistor. Output pins Vo1 and Vo2 are open drain.
Features
• Two CMOS reset circuits, one with and one without the delay function
• Reference voltage: 1.0 V
• Reference voltage accuracy: ± 50 mV
• Reference voltage hysteresis: 6% (typ.)
• Low current consumption: 1.1 μA (typ.)
• Delay time set by an external CR circuit
• Manual reset input
• Open-drain output
• TSSOP-8 (8-pin) package
• Operating temperature range: – 40 to 85°C
• Ordering Information
Part Name
RNA52A10TH5
Package Type
TSSOP-8 pin
Package Code
PTSP0008JC-B
Package
Abbreviation
T
Taping Abbreviation
(Quantity)
H (3,000 pcs / Reel)
Surface
Treatment
5 (Ni/Pd/Au)
Application
• Power-supply monitoring and resetting for microprocessors
• Power supply sequence control for microprocessors
• Desktop and laptop PCs
• PC peripheral devices such as printers
• Digital still cameras, digital video cameras, and PDAs
• Battery-driven products
• Wireless communications systems
R03DS0078EJ0200 Rev.2.00
Dec 19, 2015
Page 1 of 11
1 page  
RNA52A10T
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Test
Circuit
Supply voltage
Current consumption
Reference voltage
Reference voltage temperature
coefficient
(Reference value for design)
VDD
IDD
VREF
ΔVREF
VREF ⋅ΔTa
1.4
—
0.95
—
—
1.1
1.00
±100
5.5
19
1.05
—
V
μA
V
ppm
°C
VDD = 5.5 V
Vi1 = V i2 = 5.5 V
VDD = 3.3 V
Ta = –40 to 85°C
—
1
2
2
Vi1, Vi2 input
hysteresis voltage
Vi1, Vi2 input current
CD input threshold voltage
Vo1, Vo2
low-level output voltage
Vo1, Vo2
output leakage current
Vo2
Delay time Note1
Incomplete
discharge of
capacity CD
complete
discharge of
capacity CD
VHYS
IIN
VDLY
VOL
ILK
TDLY
TDLY0
28.5
(VREF×3%)
—
60
(VREF×6%)
0.6
94.5
(VREF×9%)
2.2
VDD×0.43 VDD×0.63 VDD×0.83
— 0.05 0.15
— 0.15 0.35
— — 100
mV VDD = 3.3 V
μA VDD = 5.5 V
Vi1 = V i2 = 5.5 V
V VDD = 3.3 V
Vi1 = V i2 = 1.2 V
VDD = 1.4V
V Vi1 = V i2 = 0 V
IOL = 0.5 mA
VDD = 3.3V
V Vi1 = V i2 = 0 V
IOL = 5 mA
nA VDD = VO1 = VO2 = 5.5 V
Vi1 = V i2 = 1.2 V
1.1 11 17 ms
VDD = 3.3 V
Vi2 = 0 V→1.2 V
7 11 17 ms CD = 0.3 μF, RD = 39 kΩ
2
3
4
5
6
7
8
8
Vo1
Rise response time
TPLH
—
30 300 μs VDD = 3.3 V
Vi1 = 0 V→1.2 V
9
Vo1, Vo2
fall response time
TPHL
—
VDD = 3.3 V
30
800 μs Vi1 = Vi2 = 1.2 V→0 V
10
CD = 0.3 μF, RD = 39 kΩ
MR low-level input voltage
VIL —
—
VDD×0.2
V VDD = 3.3 V
Vi1 = V i2 = 1.2 V
11
MR high-level
input voltage
VDD < 4.5V
VDD ≥ 4.5V
VDD×0.75
VIH
VDD×0.5
—
—
— V VDD = 3.3 V
Vi1 = V i2 = 1.2 V
— V VDD = 5.0 V
Vi1 = V i2 = 1.2 V
11
12
MR input
pull-down resistance
RMR 0.5
2
— MΩ VDD = 5.5 V
VMR = 5.5 V
13
Notes: 1. When capacitor CD is completely discharged and charging starts in the state that CD pin voltage is 0 V, the
minimum value of delay time TDLY0 is 7 ms. However, when the discharging time is short and charging starts
in the state that the voltage does not completely fall to 0 V, the minimum value of delay time TDLY is 1.1 ms.
Then, the minimum value of Low time (reset time) of Vo2 is 1.1 ms as the delay time TDLY. Refer to
Regulations for state of capacitor CD electrical discharge and delay time on page 10 for details.
2. Refer to the characteristic curves on page 6 for temperature dependence of the main characteristics.
3. Refer to pages 8 and 9 for the test circuits.
R03DS0078EJ0200 Rev.2.00
Dec 19, 2015
Page 5 of 11
5 Page 
RNA52A10T
Relation between Delay Time TDLY and External Component Values CD, RD
1000
100
10
1
1
Package Dimensions
JEITA Package Code
P-TSSOP8-4.4x3-0.65
RENESAS Code
PTSP0008JC-B
*1 D
8
5
= 1.0 μF
CD
C
D
=
0.33 μF
=
CD
0.1
CD
μF
= 0.033 μF
= 0.01
μF
CD
10
Resistance RD [kΩ]
100
1000
Previous Code
TTP-8DAV
MASS[Typ.]
0.034g
F
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
bp
Index mark
1
Z
e
4
*3 bp
xM
S
yS
Terminal cross section
(Ni/Pd/Au plating)
L1
L
Detail F
Reference Dimension in Millimeters
Symbol Min Nom Max
D 3.00 3.30
E 4.40
A2
A1 0.03 0.07 0.10
A 1.10
bp 0.15 0.20 0.25
b1
c 0.10 0.15 0.20
c1
θ 0°
8°
HE 6.20 6.40 6.60
e 0.65
x 0.13
y 0.10
Z 0.805
L 0.40 0.50 0.60
L1 1.00
R03DS0078EJ0200 Rev.2.00
Dec 19, 2015
Page 11 of 11
11 Page | ||
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| PDF Descargar | [ Datasheet RNA52A10T.PDF ] | |
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