R5F521A8BGFP Datasheet PDF - Renesas
| Part Number | R5F521A8BGFP | |
| Description | MCUs | |
| Manufacturers | Renesas | |
| Logo |  |
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Datasheet
RX21A Group
Renesas MCUs
50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit ∆Σ A/D Converter,
up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC,
MPC, RTC; up to 9 comms interfaces
R01DS0129EJ0110
Rev.1.10
Aug 28, 2014
Features
■ 32-bit RX CPU core
Max. operating frequency: 50 MHz
Capable of 78 DMIPS in operation at 50 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
Memory protection unit
On-chip debugging circuit
■ Low power design and architecture
Operation from a single 1.8-V to 3.6-V supply
(2.7 V to 3.6 V for the ΔΣ A/D converter operating
voltage)
Deep software standby mode with RTC remaining usable
Four low power modes
■ 24-bit ∆Σ A/D Converter
SNDR = 85dB
Seven ΔΣ converter units available. Seven channels can
be operated simultaneously or independently.
Up to x 64 PGA gain for differential input
■ On-chip flash memory for code, no wait states
50-MHz operation, 20-ns read cycle
No wait states for reading at full CPU speed
256-K to 512-Kbyte capacities
User code programmable via the SCI
Programmable at 1.8 V
For instructions and operands
■ On-chip data flash memory
8 Kbytes
(Number of times of reprogramming: 100,000)
Erasing and programming impose no load on the CPU.
■ On-chip SRAM, no wait states
32-K to 64-Kbyte size capacities
■ DMA
DMAC: Incorporates four channels
DTC: Four transfer modes
■ Reset and supply management
Nine types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
PLL circuit input: 4 MHz to 12.5 MHz
On-chip low- and high-speed oscillators, dedicated on-
chip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Year and month display or 32-bit second display (binary
counter) is selectable
Time capture on event-signal input through external pins
RTC capable of initiating return from deep software
standby mode
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch
PTLG0100JA-A 7×7mm, 0.65-mm pitch
■ Independent watchdog timer
125-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
■ Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock-frequency
accuracy-measurement circuit, independent watchdog
timer, functions to assist in RAM testing, etc.
■ Up to nine communications channels
SCI with many useful functions (up to five channels)
Asynchronous mode, clock synchronous mode, smart
card interface
IrDA Interface (one channel, in cooperation with the
SCI5)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (two channels)
RSPI (two channels)
■ Up to 14 extended-function timers
16-bit MTU: input capture, output compare,
complementary PWM output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
■ 10-bit A/D converter
Conversion time 2.0 μs
Self-diagnostic function and analog input disconnection
detection assistance function
■ 10-bit D/A converter
■ Analog comparator
■ General I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
■ MPC
Multiple locations are selectable for I/O pins of
peripheral functions
■ ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
■ DEU
Encryption and decryption of AES
128-, 192-, or 256-bit key length
ECB/CBC Mode
■ Temperature sensor
■ Operating temp. range
40C to +85C
40C to +105C
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 1 of 132
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RX21A Group
1. Overview
Table 1.1
Outline of Specifications (4 / 4)
Classification Module/Function
Description
Package
100-pin LQFP (PLQP0100KB-A) 14 x 14 mm, 0.5-mm pitch
80-pin LQFP (PLQP0080KB-A) 12 x 12mm, 0.5-mm pitch
64-pin LQFP (PLQP0064KB-A) 10 x 10mm, 0.5-mm pitch
100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65-mm pitch
On-chip debugging system
E1 emulator (FINE interfaces)
Note 1. Contact a Renesas Electronics sales office for more information.
Note 2. Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
Note 3. The unique ID specification and the calibration functions of the temperature sensor and the 24-Bit ∆Σ A/D converter of these
products differ from other products. For details, see following sections in the RX21A Group User’s Manual: Hardware.
Section 34.2.11, ∆Σ A/D Input Impedance Calibration Data Register (DSADIIC)
Section 34.2.12, ∆Σ A/D Gain Calibration Data Registers (DSADGmXn) (m = 0 to 6, n = 1, 2, 4, 8, 16, and 32)
Section 37.2.2, Temperature Sensor Calibration Data Registers (TSCDRn) (n = 0,1,3)
Section 37.3, Using the Temperature Sensor
Section 42.2.15, Unique ID Registers (UIDRn) (n = 0 to 3)
Table 1.2
Comparison of Functions for Different Packages
Module/Functions
Interrupt
External interrupts
DMA
DMA controller
Data transfer controller
Timers
Multi-function timer pulse unit 2
Port output enable 2
8-bit timer
Compare match timer
Realtime clock
Watchdog timer
Independent watchdog timer
Communication Serial communications interface
function
I2C bus interface
Serial peripheral interface
24-bit ∆Σ A/D converter
10-bit A/D converter
Temperature sensor
D/A converter
CRC calculator
Data encryption unit
Event link controller
Comparator A
Comparator B
Package
RX21A Group
100 Pins
80 Pins
64 Pins
NMI, IRQ0 to IRQ7
NMI, IRQ0 to IRQ2,
IRQ4 to IRQ7
4 channels (DMAC0 to DMAC3)
Supported
6 channels (MTU0 to MTU5)
POE0# to POE3#, POE8#
2 channels × 2 units
2 channels × 2 units
Supported
Supported
Supported
5 channels (SCI1, 5, 6, 8, 9) (including one channel for IrDA)
2 channels
1 channel
2 channels
7 channels
4 channels
3 channels
7 channels
(AN0 to AN6)
4 channels
(AN0, AN1, AN4,
AN5)
Supported
2 channels
—
Supported
Supported
Supported
2 channels
1 channel
2 channels
100-pin LQFP
100-pin TFLGA
80-pin LQFP
64-pin LQFP
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 5 of 132
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