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What is W9864G6KH?

This electronic component, produced by the manufacturer "Winbond", performs the same function as "1M x 4-BANKS x 16-BITS SDRAM".


W9864G6KH Datasheet PDF - Winbond

Part Number W9864G6KH
Description 1M x 4-BANKS x 16-BITS SDRAM
Manufacturers Winbond 
Logo Winbond Logo 


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W9864G6KH
1M 4 BANKS 16 BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION.......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. ORDER INFORMATION ............................................................................................................. 3
4. PIN CONFIGURATION ............................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1 Power Up and Initialization.............................................................................................. 7
7.2 Programming Mode Register Set command .................................................................. 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Command .............................................................................................................. 8
7.7 Read Interrupted by a Read............................................................................................ 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode..................................................................... 9
7.13 Addressing Sequence of Interleave Mode ...................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode........................................................................................................ 11
7.18 No Operation Command ............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
9. ELECTRICAL CHARACTERISTICS ......................................................................................... 13
9.1 Absolute Maximum Ratings .......................................................................................... 13
9.2 Recommended DC Operating Conditions .................................................................... 13
9.3 Capacitance .................................................................................................................. 13
Publication Release Date: Nov. 12, 2013
- 1 - Revision A02

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W9864G6KH equivalent
W9864G6KH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
23 ~ 26, 22,
29 ~35
A0A11
Address
Row address: A0A11. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
20, 21
BS0, BS1
Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
DQ0DQ15
51, 53
Data
Input/ Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
19 CS Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
18
RAS
Row Address
Strobe
the clock RAS , CAS and WE define the
operation to be executed.
17
CAS
Column
Address Strobe Referred to RAS
16
39, 15
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
WE
UDQM
LDQM
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Write Enable Referred to RAS
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power
Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside
DRAM.
Power for I/O Separated power from VDD, to improve DQ noise
buffer
immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection.
Publication Release Date: Nov. 12, 2013
- 5 - Revision A02


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Featured Datasheets

Part NumberDescriptionMFRS
W9864G6KHThe function is 1M x 4-BANKS x 16-BITS SDRAM. WinbondWinbond

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