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PDF S34ML02G2 Data sheet ( Hoja de datos )

Número de pieza S34ML02G2
Descripción NAND Flash Memory
Fabricantes Cypress Semiconductor　
Logotipo Cypress Semiconductor Logotipo



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S34ML01G2
S34ML02G2
S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC
NAND Flash Memory for Embedded
Distinctive Characteristics
Density
– 1 Gb / 2 Gb / 4 Gb
Architecture
– Input / Output Bus Width: 8 bits / 16 bits
– Page size:
– ×8:
1 Gb: (2048 + 64) bytes; 64-byte spare area
2 Gb / 4 Gb: (2048 + 128) bytes; 128-byte spare area
– ×16:
1 Gb: (1024 + 32) words; 32-word spare area
2 Gb / 4 Gb (1024 + 64) words; 64-word spare area
– Block size: 64 Pages
– ×8:
1 Gb: 128 KB+ 4 KB
2 Gb / 4 Gb: 128 KB + 8 KB
– ×16
1 Gb: 64k + 2k words
2 Gb / 4 Gb: 64k + 4k words
– Plane size
– ×8
1 Gb: 1024 blocks per plane or (128 MB + 4 MB
2 Gb: 1024 blocks per plane or (128 MB + 8 MB
4 Gb: 2048 blocks per plane or (256 MB + 16 MB
– ×16
1 Gb: 1024 blocks per plane or (64M + 2M) words
2 Gb: 1024 Blocks per Plane or (64M + 4M) words
4 Gb: 2048 Blocks per Plane or (128M + 8M) words
– Device Size
– 1 Gb: 1 plane per device or 128 Mbyte
– 2 Gb: 2 planes per device or 256 Mbyte
– 4 Gb: 2 planes per device or 512 Mbyte
NAND Flash interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data, and Commands multiplexed
Supply Voltage
– 3.3-V device: VCC = 2.7 V ~ 3.6 V
Security
– One Time Programmable (OTP) area
– Serial number (unique ID) (Contact factory for support)
– Hardware program/erase disabled during power transition
Additional features
– 2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
– Supports Copy Back Program
– 2 Gb and 4 Gb parts support Multiplane Copy Back Program
– Supports Read Cache
Electronic signature
– Manufacturer ID: 01h
Operating temperature
– Industrial: –40 °C to 85 °C
– Industrial Plus: –40 °C to 105 °C
Performance
Page Read / Program
– Random access: 25 µs (Max) (S34ML01G2)
– Random access: 30 µs (Max) (S34ML02G2, S34ML04G2)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 300 µs (Typ)
Block Erase (S34ML01G2)
– Block Erase time: 3 ms (Typ)
Block Erase / Multiplane Erase (S34ML02G2, S34ML04G2)
– Block Erase time: 3.5 ms (Typ)
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes (×8) or 264 words (×16))
– 10 Year Data retention (Typ)
– For one plane structure (1-Gb density)
– Block zero is valid and will be valid for at least 1,000 program-
erase cycles with ECC
– For two plane structures (2-Gb and 4-Gb densities)
– Blocks zero and one are valid and will be valid for at least 1,000
program-erase cycles with ECC
Package options
– Pb-free and low halogen
– 48-Pin TSOP 12 × 20 × 1.2 mm
– 63-Ball BGA 9 × 11 × 1 mm
– 67-Ball BGA 8 × 6.5 × 1 mm (S34ML01G2, S34ML02G2)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00499 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 30, 2016

1 page




S34ML02G2 pdf
S34ML01G2
S34ML02G2
S34ML04G2
1.2
Connection Diagram
Figure 1.2 48-Pin TSOP1 Contact ×8, ×16 Device
x16 x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1
12
13
24
NAND Flash
TSOP1
x8 x16
48 VSS(1) VSS
NC I/O15
NC I/O14
NC I/O13
I/O7 I/O7
I/O6 I/O6
I/O5 I/O5
I/O4 I/O4
NC I/O12
VCC(1) VCC
NC NC
37 VCC VCC
36 VSS VSS
NC NC
VCC(1) VCC
NC I/011
I/O3 I/O3
I/O2 I/O2
I/O1 I/O1
I/O0 I/O0
NC I/O10
NC I/O9
NC I/O8
25 VSS(1) VSS
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 1.3 63-BGA Contact, ×8 Device (Balls Down, Top View)
A1 A2
NC NC
A9 A10
NC NC
B1 B9 B10
NC NC NC
C3
WP#
C4
ALE
C5
VSS
C6
CE#
C7
WE#
C8
RB#
D3 D4 D5 D6 D7 D8
VCC (1) RE# CLE NC NC NC
E3 E4 E5 E6 E7 E8
NC NC NC NC NC NC
F3 F4 F5 F6 F7 F8
NC NC NC NC VSS (1) NC
G3 G4 G5 G6 G7 G8
NC VCC (1) NC
NC
NC
NC
H3 H4 H5 H6 H7 H8
NC I/O0 NC NC NC Vcc
J3 J4 J5 J6 J7 J8
NC I/O1 NC VCC I/O5 I/O7
K3 K4 K5 K6 K7 K8
VSS I/O2 I/O3 I/O4 I/O6 VSS
L1 L2
NC NC
L9 L10
NC NC
M1 M2
NC NC
M9 M10
NC NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Document Number: 002-00499 Rev. *N
Page 5 of 76

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S34ML02G2 arduino
S34ML01G2
S34ML02G2
S34ML04G2
1.6 Addressing
1.6.1
S34ML01G2
Table 1.3 Address Cycle Map — 1 Gb Device
Bus Cycle I/O [15:8] (5)
I/O0
I/O1
I/O2
I/O3
I/O4 I/O5 I/O6 I/O7
×8
1st / Col. Add.1
—
A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
2nd / Col. Add. 2
—
A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) Low
Low
Low
Low
3rd / Row Add. 1
—
A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5) A18 (BA0) A19 (BA1)
4th / Row Add. 2
—
A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8) A27 (BA9)
×16
1st / Col. Add.1
Low
A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
2nd / Col. Add. 2
Low
A8 (CA8) A9 (CA9) A10 (CA10)
Low
Low Low Low Low
3rd / Row Add. 1
Low
A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A15 (PA4) A16 (PA5) A17 (BA0) A18 (BA1)
4th / Row Add. 2
Low
A19 (BA2) A20 (BA3) A21 (BA4) A22 (BA5) A23 (BA6) A24 (BA7) A25 (BA8) A26 (BA9)
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. BAx = Block Address bit.
4. Block address concatenated with page address = actual page address, also known as the row address.
5. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18 - A27: block address
For the x16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17 - A26: block address
1.6.2
S34ML02G2
Table 1.4 Address Cycle Map — 2 Gb Device
Bus Cycle I/O [15:8] (6) I/O0
I/O1
I/O2
I/O3 I/O4 I/O5 I/O6 I/O7
×8
1st / Col. Add.1 — A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
2nd / Col. Add. 2
—
A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) Low
Low
Low
Low
3rd / Row Add. 1
—
A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5)
A18
(PLA0)
A19 (BA0)
4th / Row Add. 2 — A20 (BA1) A21 (BA2) A22 (BA3) A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8)
5th / Row Add. 3 — A28 (BA9) Low
Low
Low Low Low Low Low
×16
1st / Col. Add.1 Low A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
Document Number: 002-00499 Rev. *N
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11 Page







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