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Winbond - LPDDR2-S4B 512Mb

Numéro de référence W979H2KB
Description LPDDR2-S4B 512Mb
Fabricant Winbond 
Logo Winbond 





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W979H2KB fiche technique
W979H6KB / W979H2KB
LPDDR2-S4B 512Mb
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................................................ 6
2. FEATURES.................................................................................................................................................................... 6
3. ORDER INFORMATION................................................................................................................................................ 7
4.
4.1
4.2
PIN CONFIGURATION .................................................................................................................................................. 8
134 Ball VFBGA............................................................................................................................................................. 8
168 Ball WFBGA............................................................................................................................................................ 9
5.
5.1
5.2
PIN DESCRIPTION ..................................................................................................................................................... 10
Basic Functionality ....................................................................................................................................................... 10
Addressing Table ......................................................................................................................................................... 11
6. BLOCK DIAGRAM ....................................................................................................................................................... 12
7. FUNCTIONAL DESCRIPTION..................................................................................................................................... 13
7.1 Simplified LPDDR2 State Diagram .............................................................................................................................. 13
7.1.1
Simplified LPDDR2 Bus Interface State Diagram ............................................................................................................14
7.2 Power-up, Initialization, and Power-Off........................................................................................................................ 15
7.2.1
Power Ramp and Device Initialization .............................................................................................................................15
7.2.2
Timing Parameters for Initialization .................................................................................................................................17
7.2.3
Power Ramp and Initialization Sequence ........................................................................................................................17
7.2.4
Initialization after Reset (without Power ramp) ................................................................................................................18
7.2.5
Power-off Sequence ........................................................................................................................................................18
7.2.6
Timing Parameters Power-Off .........................................................................................................................................18
7.2.7
Uncontrolled Power-Off Sequence ..................................................................................................................................18
7.3 Mode Register Definition.............................................................................................................................................. 19
7.3.1
Mode Register Assignment and Definition.......................................................................................................................19
7.3.1.1
Mode Register Assignment...................................................................................................................................19
7.3.2
MR0_Device Information (MA[7:0] = 00H).......................................................................................................................20
7.3.3
MR1_Device Feature 1 (MA[7:0] = 01H) .........................................................................................................................20
7.3.3.1
Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC) ...............................................21
7.3.3.2
Non Wrap Restrictions ..........................................................................................................................................21
7.3.4
MR2_Device Feature 2 (MA[7:0] = 02H) .........................................................................................................................22
7.3.5
MR3_I/O Configuration 1 (MA[7:0] = 03H).......................................................................................................................22
7.3.6
MR4_Device Temperature (MA[7:0] = 04H) ....................................................................................................................22
7.3.7
MR5_Basic Configuration 1 (MA[7:0] = 05H)...................................................................................................................23
7.3.8
MR6_Basic Configuration 2 (MA[7:0] = 06H)...................................................................................................................23
7.3.9
MR7_Basic Configuration 3 (MA[7:0] = 07H)...................................................................................................................23
7.3.10
MR8_Basic Configuration 4 (MA[7:0] = 08H)...................................................................................................................23
7.3.11
MR9_Test Mode (MA[7:0] = 09H)....................................................................................................................................23
7.3.12
MR10_Calibration (MA[7:0] = 0AH) .................................................................................................................................24
7.3.13
MR16_PASR_Bank Mask (MA[7:0] = 10H) .....................................................................................................................24
7.3.14
MR32_DQ Calibration Pattern A (MA[7:0] = 20H) ...........................................................................................................25
7.3.15
MR40_DQ Calibration Pattern B (MA[7:0] = 28H) ...........................................................................................................25
7.3.16
MR63_Reset (MA[7:0] = 3FH): MRW only.......................................................................................................................25
7.4 Command Definitions and Timing Diagrams................................................................................................................ 25
7.4.1
Activate Command ..........................................................................................................................................................25
7.4.1.1
Activate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2......................................................................................25
7.4.1.2
Command Input Setup and Hold Timing...............................................................................................................26
7.4.1.3
CKE Input Setup and Hold Timing ........................................................................................................................26
7.4.2
Read and Write Access Modes .......................................................................................................................................27
7.4.3
Burst Read Command .....................................................................................................................................................27
7.4.3.1
Data Output (Read) Timing (tDQSCKmax) ...........................................................................................................27
7.4.3.2
Data Output (Read) Timing (tDQSCKmin)............................................................................................................28
7.4.3.3
Burst Read: RL = 5, BL = 4, tDQSCK > tCK .........................................................................................................28
7.4.3.4
Burst Read: RL = 3, BL = 8, tDQSCK < tCK .........................................................................................................29
Publication Release Date: Jan. 19, 2015
Revision: A01-002
-1-

PagesPages 30
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