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PDF ACE25Q800G Data sheet ( Hoja de datos )
| Número de pieza | ACE25Q800G | |
| Descripción | 8M BIT SPI NOR FLASH | |
| Fabricantes | ACE Technology | |
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ACE25Q800G
8M BIT SPI NOR FLASH Memory Series
Description
The ACE25Q800G is 8M-bit Serial Peripheral Interface(SPI) Flash memory, and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (/WP), and I/O3 (/HOLD).
The Dual I/O data is transferred with speed of 216Mbits/s and the Quad I/O & Quad output data is
transferred with speed of 434Mbits/s. The device uses a single low voltage power
supply, ranging from 2.7 Volt to 3.6 Volt.
Additionally, the device supports JEDEC standard manufacturer and device ID and three
256-bytes Security Registers..
Features
● Serial Peripheral Interface (SPI)
- Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD
- Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD
- Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3
● Read
- Normal Read (Serial): 50MHz clock rate
- Fast Read (Serial): 108MHz clock rate
- Dual/Quad (Multi-I/O) Read: 108MHz clock rate
● Program
- Serial-input Page Program up to 256bytes
-Program Suspend and Resume
● Erase
- Block erase (64/32 KB)
- Sector erase (4 KB)
- Chip erase
- Erase Suspend and Resume
● Program/Erase Speed
- Page Program time: 0.7ms typical
- Sector Erase time: 60ms typical
- Block Erase time: 0.2/0.4s typical
- Chip Erase time: 7s typical
● Flexible Architecture
-Sector of 4K-byte
-Block of 32/64K-byte
● Low Power Consumption
- 20mA maximum active current
- 5uA maximum power down current
VER 1.1 1
1 page  
ACE25Q800G
8M BIT SPI NOR FLASH Memory Series
Device Operation
Standard SPI Instructions
The ACE25Q800G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK.
Dual SPI Instructions
The ACE25Q800G supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual
I/O Fast Read” (3BH and BBH) instructions. These instructions allow data to be transferred to or from
the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and
SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI Instructions
The ACE25Q800G supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O
Fast Read” (6BH, EBH) instructions. These instructions allow data to be transferred t-o or from the
device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO
pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
Operation Features
Supply Voltage
Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified
[VCC(min), VCC(max)] range must be applied (see operating ranges of page 37). In order to secure a stable DC
supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to
100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission
of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS)
line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to
VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level
sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip
Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation.
Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR)
circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on
reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in operating ranges of
page 37).
When VCC has passed the POR threshold, the device is reset.
VER 1.1 5
5 Page 
ACE25Q800G
8M BIT SPI NOR FLASH Memory Series
Table 7 ACE25Q800G Status Register Memory Protection(CMP=1)
Status Register Content
Memory Content
SEC TB BP2 BP1 BP0 Blocks
Addresses
Density
Portion
X X0
0
0 0 to 15 000000H-0FFFFFH
1MB
ALL
0
00
0
1
0 to 14 000000H-0EFFFFH
960KB Lower 15/16
0
00
1
0 0 to 13 000000H-0DFFFFH 896KB
Lower 7/8
0
00
1
1 0 to 11 000000H-0BFFFFH 768KB
Lower 3/4
0
01
0
0
0 to 7
000000H-07FFFFH
512KB
Lower 1/2
0 1 0 0 1 1 to 15 010000H-0FFFFFH 960KB Upper 15/16
0
10
1
0
2 to 15 020000H-0FFFFFH
896KB
Upper 7/8
0
10
1
1
4 to 15 040000H-0FFFFFH
768KB
Upper 3/4
0
11
0
0 8 to 15 080000H-0FFFFFH 512KB
Upper 1/2
0 X 1 0 1 NONE
NONE
NONE
NONE
X X 1 1 X NONE
NONE
NONE
NONE
1 0 0 0 1 0 to 15 000000H-0FEFFFH 1020KB L-255/256
1 0 0 1 0 0 to 15 000000H-0FDFFFH 1016KB L-127/128
1
00
1
1 0 to 15 000000H-0FBFFFH 1008KB
L-163/64
1
01
0
X 0 to 15 000000H-0F7FFFH 992KB
L-31/32
1 1 0 0 1 0 to 15 001000H-0FFFFFH 1020KB U-255-256
1 1 0 1 0 0 to 15 002000H-0FFFFFH 1016KB U-127/128
1 1 0 1 1 0 to 15 004000H-0FFFFFH 1008KB U-63/64
1
11
0
X 0 to 15 008000H-0FFFFFH 992KB
U-31/32
Device Identification
Three legacy Instructions are supported to access device identification that can indicate the
manufacturer, device type, and capacity (density). The returned data bytes provide the information as
shown in the below table.
Table 8 ACE25Q800G ID Definition table
Operation Code
M7-M0
9FH E0
90H E0
ABH
ID15-ID8
40
ID7-ID0
14
13
13
VER 1.1 11
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