PDF M5M5V5636UG-16 Data sheet ( Hoja de datos )

Número de pieza	M5M5V5636UG-16
Descripción	18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Fabricantes	Renesas
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No Preview Available ! DESCRIPTION The M5M5V5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Renesas's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5V5636UG operates on 3.3V power/ 2.5V I/O supply or a single 3.3V power supply and are 3.3V CMOS compatible. The M5M5V5636UG also operates on a single 2.5V power supply and is also 2.5V CMOS compatible. Therefore the M5M5V5636UG can replace the M5M5T5636UG. The M5M5V5636UG-16 operates at 167MHz or 133MHz and is guaranteed both AC DC electrical characteristics of 167MHz and those of 133MHz. FEATURES • Fully registered inputs and outputs for pipelined operation • Fast clock speed: 167 and 133 MHz • Fast access time: 3.8 and 4.2 ns • Single 3.3V -5% and +5% power supply VDD • Separate VDDQ for 3.3V or 2.5V I/O • Single 2.5V -5% and +5% power supply VDD • Individual byte write (BWa# - BWd#) controls may be tied LOW • Single Read/Write control pin (W#) • CKE# pin to enable clock and suspend operations • Internally self-timed, registers outputs eliminate the need to control G# • Snooze mode (ZZ) for power down • Linear or Interleaved Burst Modes • Three chip enables for simple depth expansion • JTAG boundary scan support Renesas LSIs M5M5V5636UG – 16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM PACKAGE 165(11x15) bump BGA Body Size (13mm x 15mm) Bump Pitch 1.0mm APPLICATION High-end networking products that require high bandwidth, such as switches and routers. FUNCTION Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#, BWd#) and Read/Write (W#). Write operations are controlled by the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. Asynchronous inputs include Output Enable (G#), Clock (CLK) and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the SRAM in the power-down state.The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst. All read, write and deselect cycles are initiated by the ADV LOW input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input. PART NAME TABLE M5M5V5636UG-16 Operate frequency 167MHz 133MHz Access 3.8ns 4.2ns 1/25 Cycle 6.0ns 7.5ns Active Current (max.) 380mA 350mA Standby Current (max.) 30mA 30mA M5M5V5636UG-16 REV.2.0 1 page Renesas LSIs M5M5V5636UG – 16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM DC OPERATED TRUTH TABLE Name Input Status Operation LBO# HIGH or NC LOW Interleaved Burst Sequence Linear Burst Sequence Note4. LBO# is DC operated pin. Note5. NC means No Connection. Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence. BURST SEQUENCE TABLE Interleaved Burst Sequence (when LBO# = HIGH or NC) Operation A18~A2 First access, latch external address A18~A2 Second access(first burst address) latched A18~A2 Third access(second burst address) latched A18~A2 Fourth access(third burst address) latched A18~A2 Linear Burst Sequence (when LBO# = LOW) Operation A18~A2 First access, latch external address Second access(first burst address) Third access(second burst address) A18~A2 latched A18~A2 latched A18~A2 Fourth access(third burst address) latched A18~A2 Note7. The burst sequence wraps around to its initial state upon completion. 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 A1,A0 0,1 1,0 0,0 1,1 1,1 0,0 1,0 0,1 A1,A0 0,1 1,0 1,0 1,1 1,1 0,0 0,0 0,1 1,1 1,0 0,1 0,0 1,1 0,0 0,1 1,0 TRUTH TABLE Address E1# E2 E3# ZZ ADV W# BWx# G# CKE# CLK DQ used Operation H X X L L X X X L L->H High-Z None Deselect Cycle X L X L L X X X L L->H High-Z None Deselect Cycle X X H L L X X X L L->H High-Z None Deselect Cycle X X X L H X X X L L->H High-Z None Continue Deselect Cycle L H L L L H X L L L->H Q External Read Cycle, Begin Burst X X X L H X X L L L->H Q Next Read Cycle, Continue Burst L H L L L H X H L L->H High-Z External NOP/Dummy Read, Begin Burst X X X L H X X H L L->H High-Z Next Dummy Read, Continue Burst L H L L L L L X L L->H D External Write Cycle, Begin Burst X X X L H X L X L L->H D Next Write Cycle, Continue Burst LH L L L L H X L L->H High-Z None NOP/Write Abort, Begin Burst X X X L H X H X L L->H High-Z Next Write Abort, Continue Burst X X X L X X X X H L->H - Current Ignore Clock edge, Stall X X X H X X X X X X High-Z None Snooze Mode Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL. Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more Synchronous Byte Write Enables are LOW. Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5/25 M5M5V5636UG-16 REV.2.0 5 Page (2)TIMING CHARACTERISTICS Symbol Parameter Renesas LSIs M5M5V5636UG – 16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM Limits 167MHz 133MHz -16 -16 Min Max Min Max Unit tKHKH tKHKL tKLKH Clock cycle time Clock HIGH time Clock LOW time 6.0 7.5 ns 2.7 3.0 ns 2.7 3.0 ns tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX1 tGHQZ Clock HIGH to output valid Clock HIGH to output invalid Clock HIGH to output in LOW-Z Clock HIGH to output in High-Z G# to output valid G# to output in Low-Z G# to output in High-Z 3.8 4.2 ns 1.5 1.5 ns 1.5 1.5 ns 1.5 3.8 1.5 4.2 ns 3.8 4.2 ns 0.0 0.0 ns 3.8 4.2 ns tAVKH tckeVKH tadvVKH tWVKH tBVKH tEVKH tDVKH Address valid to clock HIGH CKE# valid to clock HIGH ADV valid to clock HIGH Write valid to clock HIGH Byte write valid to clock HIGH (BWa#~BWd#) Enable valid to clock HIGH (E1#,E2,E3#) Data In valid clock HIGH 1.2 1.2 ns 1.2 1.2 ns 1.2 1.2 ns 1.2 1.2 ns 1.2 1.2 ns 1.2 1.2 ns 1.2 1.2 ns tKHAX tKHckeX tKHadvX tKHWX tKHBX tKHEX tKHDX Clock HIGH to Address don’t care Clock HIGH to CKE# don’t care Clock HIGH to ADV don’t care Clock HIGH to Write don’t care Clock HIGH to Byte Write don’t care (BWa#~BWb#) Clock HIGH to Enable don’t care (E1#,E2,E3#) Clock HIGH to Data In don’t care 0.8 0.8 ns 0.8 0.8 ns 0.8 0.8 ns 0.8 0.8 ns 0.8 0.8 ns 0.8 0.8 ns 0.8 0.8 ns tZZS ZZ standby 2tKHKH tZZREC ZZ recovery 2tKHKH Note25.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix. Note26.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted. Note27. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled. Note28.LBO# is static and must not change during normal operation. 2tKHKH 2tKHKH ns ns 11/25 M5M5V5636UG-16 REV.2.0 11 Page

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