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PDF R2A20150SA Data sheet ( Hoja de datos )
| Número de pieza | R2A20150SA | |
| Descripción | 8-bit I/O Expander | |
| Fabricantes | Renesas | |
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New Product
R2A20150NP/SA
8-bit I/O Expander for I2C BUS (Corresponds to Fast mode)
R03DS0012EJ0100
Rev.1.00
2011.09.05
Description
The R2A20150NP/SA is a CMOS 8-bit I/O expander, which has serial to parallel and parallel to serial
data converting functions.
It can communicate with a microcontroller via few wiring thanks to the adoption of the 2-wire I2C BUS.
Maximum 8 ICs can be connected to a bus by using 3-chip select pins, so that it is possible to handle up
to 64 bits data.
Features
Simple 2-wire (SCL and SDA) communication with a microcontroller.
8-bit data conversion between serial and parallel by I2C BUS.
Corresponds to Fast mode (400kHz) of I2C BUS specification.
Possible to set input and output each bit separately.
By using three chip select pins (CS0,CS1,CS2), R2A20150 can connect with the same BUS line
to maximum 8 pieces.
Very small package line-up QFN-16 and TSSOP-16.
Application
I/O port expansion of Microcomputer.
Data conversion from serial to parallel and from parallel to serial in peripheral of Microcomputer.
Block Diagram
CS0
16
14
CS1
15
13
CS2
14
12
Number for TSSOP package
Number for QFN package
SCL 2 16
SDA 3 1
VDD 13 11
GND 8 6
Reset
POWER ON
RESET
I2C BUS
TRANSCIEVER
SHIFT
RESISTOR
Output Data
Input/Output
88
8
OUTPUT
DATA LATCH
I/O SETTING
DATA LATCH
INPUT
DATA LATCH
88
I/O PORT
8
Input Data
15 1 SO
10 9 8 7 5 4 3 2
12 11 10
9
7
6
5
4
D7 D6 D5 D4 D3 D2 D1 D0
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 1 of 10
1 page  
R2A20150NP/SA
New Product
Functional Blocks
I2C BUS Interface
The I2C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection
by receiving SDA,SCL,CS0,CS1 and CS2 signals and then the latch pulse, dedicated to each data latch
are generated.
Data Latch
This IC has 3 types of data latch: the I/O setting data latch, the input data latch and the output data latch
and each latch is controlled by the I2C BUS interface.
I/O setting data latch
These latches set input-state or output-state of each parallel data terminals (D0 to D7). They are
set at the next byte after receiving the slave address byte in the write mode from the master.
In case this latch is set to high, the data is transferred from the I2C BUS interface to the parallel
data terminals. In the opposite transmission: from the parallel data terminals to the I2C BUS,
it is set to low.
Output data latch
In the write mode, the data from the I2C BUS to the parallel data terminals is latched.
When the master transmits output data after a setting in write mode, the output data is taken into
the latch.
Input data latch
In the read mode, the data of parallel data terminals is latched in the input data latches. The input
data is taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock.
The latched data is output to the master through the sift resistor. On the output terminal assigned by
the I/O setting latch, the input data latch takes the state of the output terminal.
Parallel Input/Output Port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance
and is able to accept an input. In another case I/O setting latch is set to high (output mode), each parallel
terminal output a data according to the state of the output data latch.
Serial Output Port
The parallel data from each parallel terminal are conversion to 8bit serial data and output to SO terminal.
Without serial output mode, SO terminal goes to low output.
Power on Reset
When the power is turned on, each latch is reset (initialize) and then the parallel data I/O terminals
become hi-impedance (input mode).
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 5 of 10
5 Page 
Notice
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