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Número de pieza | HD74HC590 | |
Descripción | 8-bit Binary Counter/Register | |
Fabricantes | Renesas | |
Logotipo | ||
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No Preview Available ! HD74HC590
8-bit Binary Counter/Register (with 3-state outputs)
REJ03D0632-0200
(Previous ADE-205-512)
Rev.2.00
Mar 30, 2006
Description
This device each contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel
outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a
direct clear input CCLR and a count enable input CCKEN. For cascading a ripple carry output RCO is provided.
Expansion is easily accomplished by tying RCO of the first stage to CCKEN of the second stage, etc.
Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the
counter state will always be one count ahead of the register, Internal circuitry prevents clocking from the clock enable.
Features
• High Speed Operation: tpd (RCK to Q) = 18.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC590P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74HC590FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Function Table
G RCK
HX
LX
X
X
XX
XX
XX
XX
Inputs
CCLR
X
X
X
X
L
H
H
H
CCKEN
X
X
X
X
X
L
L
H
RCO = QA’•QB’•QC’•QD’•QE’•QF’•QG’•QH’• (CCKEN)
(QA’ to QH’: Output of Internal Counter)
CCK
X
X
X
X
X
X
Function
Q output disabled
Q output enabled
Contents of counter stored to register
No change in register
Counter clear
Count up
No count
No count
Rev.2.00 Mar 30, 2006 page 1 of 9
1 page HD74HC590
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Item
Maximum clock
frequency
Propagation delay
time
Output enable
time
Output disable
time
Pulse width
Removal time
Setup time
Hold time
Output rise/fall
time
Input capacitance
Symbol VCC (V)
fmax 2.0
4.5
6.0
tPLH 2.0
tPHL 4.5
6.0
tPLH 2.0
4.5
6.0
tPLH 2.0
tPHL 4.5
6.0
tZL 2.0
tZH 4.5
6.0
tLZ 2.0
tHZ 4.5
6.0
tw 2.0
4.5
6.0
trem 2.0
4.5
6.0
tsu 2.0
4.5
6.0
2.0
4.5
6.0
th 2.0
4.5
6.0
tTLH 2.0
tTHL 4.5
6.0
tTLH 2.0
tTHL 4.5
6.0
Cin —
Ta = 25°C
Min Typ Max
—— 5
— — 25
— — 29
— — 200
— 18 40
— — 34
— — 250
— 17 50
— — 43
— — 200
— 18 40
— — 34
— — 150
— 16 30
— — 26
— — 150
— 17 30
— — 26
80 — —
16 6 —
14 — —
5 ——
5 ——
5 ——
100 — —
20 –3 —
17 — —
200 — —
40 10 —
34 — —
5 ——
5 ——
5 ——
— — 60
— 4 12
— — 10
— — 75
— 5 15
— — 13
— 5 10
Ta = –40 to +85°C
Min Max Unit
Test Conditions
— 4 MHz
— 20
— 24
— 250 ns CCK to RCO
— 50
— 43
— 315 ns CCLR to RCO
— 63
— 54
— 250 ns RCK to Q
— 50
— 43
— 190 ns
— 39
— 33
— 190 ns
— 38
— 33
100 — ns
20 —
17 —
5 — ns CCLR to CCK
5—
5—
125 — ns CCKEN to CCK
25 —
21 —
250 — ns CCK to RCK
50 —
43 —
5 — ns CCKEN to CCK
5—
CCK to RCK
5—
— 75 ns Q
— 15
— 13
— 95 ns RCO
— 19
— 16
— 10 pF
Rev.2.00 Mar 30, 2006 page 5 of 9
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet HD74HC590.PDF ] |
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