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PDF HD74HC534 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC534 | |
| Descripción | Octal D-type Flip-Flops | |
| Fabricantes | Renesas | |
| Logotipo |  |
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HD74HC374, HD74HC534
Octal D-type Flip-Flops (with 3-state outputs)
Octal D-type Flip-Flops (with inverted 3-state outputs)
REJ03D0620-0200
(Previous ADE-205-499)
Rev.2.00
Mar 30, 2006
Description
These devices are positive edge triggered flip-flops. The difference between HD74HC374 and HD74HC534 is only
that the former is a true outputs and the latter is a false outputs. Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive going transitions of the clock (CK) input. When a high logic
level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements.
Features
• High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC374P
HD74HC534P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74HC374FPEL
HD74HC534FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
HD74HC534RPEL
SOP-20 pin (JEDEC)
PRSP0020DC-A
(FP-20DBV)
RP
HD74HC374TELL TSSOP-20 pin
PTSP0020JB-A
(TTP-20DAV)
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Output Control
Clock
D
LH
LL
LLX
HXX
Note: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
HD74HC374
Q
H
L
No change
Z
HD74HC534
Q
L
H
No change
Z
Rev.2.00 Mar 30, 2006 page 1 of 8
1 page  
HD74HC374, HD74HC534
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Item
Maximum clock
frequency
Propagation delay
time
Output enable
time
Output disable
time
Setup time
Hold time
Pulse width
Output rise/fall
time
Input capacitance
Symbol VCC (V)
fmax 2.0
4.5
6.0
tPHL 2.0
tPLH 4.5
6.0
tZL 2.0
4.5
6.0
tZH 2.0
4.5
6.0
tLZ 2.0
4.5
6.0
tHZ 2.0
4.5
6.0
tsu 2.0
4.5
6.0
th 2.0
4.5
6.0
tw 2.0
4.5
6.0
tTLH 2.0
tTHL 4.5
6.0
Cin —
Ta = 25°C
Min Typ Max
—— 6
— — 30
— — 35
— — 140
— 18 28
— — 24
— — 150
— 11 30
— — 26
— — 150
— 14 30
— — 26
— — 150
— 13 30
— — 26
— — 150
— 16 30
— — 26
100 — —
20 1 —
17 — —
25 — —
5 1—
5 ——
80 — —
16 6 —
14 — —
— — 60
— 4 12
— — 10
— 5 10
Ta = –40 to +85°C
Min Max Unit
Test Conditions
— 5 MHz
— 24
— 28
— 175 ns
— 35
— 30
— 190 ns
— 38
— 33
— 190 ns
— 38
— 33
— 190 ns
— 38
— 33
— 190 ns
— 38
— 33
125 — ns Data to Clock
25 —
21 —
31 — ns Clock to Data
6—
6—
100 — ns Clock or Output control
20 —
17 —
— 75 ns
— 15
— 13
— 10 pF
Test Circuit
VCC
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
VCC
Output
OC 1Q to 8Q
or
1Q to 8Q
1D to 8D
Clock
1 k Ω S1
CL =
50 pF
OPEN
GND
VCC
TEST
tPLH / t PHL
tZH/ t HZ
tZL / t LZ
S1
OPEN
GND
VCC
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 5 of 8
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HD74HC534.PDF ] | |
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