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PDF HD74HC373 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC373 | |
| Descripción | Octal D-type Transparent Latches | |
| Fabricantes | Renesas | |
| Logotipo |  |
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HD74HC373, HD74HC533
Octal D-type Transparent Latches (with 3-state outputs)
Octal D-type Transparent Latches (with inverted 3-state outputs)
REJ03D0619-0300
Rev.3.00
Mar 25, 2009
Description
When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of
HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of
the storage elements.
Features
• High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
HD74HC373P
HD74HC533P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
HD74HC373FPEL
HD74HC533FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
HD74HC373RPEL
HD74HC533RPEL
SOP-20 pin (JEDEC)
PRSP0020DC-A
(FP-20DBV)
HD74HC373TELL
TSSOP-20 pin
PTSP0020JB-A
(TTP-20DAV)
Note: Please consult the sales office for the above package availability.
Package
Abbreviation
P
Taping Abbreviation
(Quantity)
—
FP EL (2,000 pcs/reel)
RP EL (1,000 pcs/reel)
T ELL (2,000 pcs/reel)
Function Table
Output Control
Enable G
D
Note:
L HH
LHL
LLX
HXX
1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
HD74HC373
Q
H
L
No change
Z
HD74HC533
Q
L
H
No change
Z
REJ03D0619-0300 Rev.3.00 Mar 25, 2009
Page 1 of 9
1 page  
HD74HC373, HD74HC533
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Item
Propagation delay
time
Output enable
time
Output disable
time
Setup time
Hold time
Pulse width
Output rise/fall
time
Input capacitance
Symbol VCC (V)
2.0
tPLH 4.5
tPHL 6.0
2.0
tPLH 4.5
tPHL 6.0
2.0
tZL 4.5
6.0
2.0
tZH 4.5
6.0
2.0
tLZ 4.5
6.0
2.0
tHZ 4.5
6.0
2.0
tsu 4.5
6.0
2.0
th 4.5
6.0
2.0
tw 4.5
6.0
2.0
tTLH 4.5
tTHL 6.0
Cin —
Ta = 25°C
Min Typ
— — 150
— 18 30
— — 26
— — 125
— 16 25
— — 21
— — 150
— 12 30
— — 26
— — 150
— 15 30
— — 26
— — 150
— 13 30
— — 26
— — 150
— 16 30
— — 26
100 — —
20 1 —
17 — —
50 — —
10 1 —
9 ——
80 — —
16 6 —
14 — —
— — 60
— 4 12
— — 10
— 5 10
Ta = –40 to +85°C Unit
Max
Test Conditions
— 190
— 38 ns G to Q
— 33
— 155
— 31 ns D to Q
— 26
— 190
— 38 ns
— 33
— 190
— 38 ns
— 33
— 190
— 38 ns
— 33
— 190
— 38 ns
— 33
125 —
25 — ns
21 —
65 —
13 — ns
11 —
100 —
20 — ns
17 —
— 75
— 15 ns
— 13
— 10 pF
Test Circuit
VCC
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
VCC
Output
OC 1Q to 8Q
or
1Q to 8Q
1D to 8D
Enable G
1 k Ω S1
CL =
50 pF
OPEN
GND
VCC
TEST
tPLH / t PHL
tZH/ t HZ
tZL / t LZ
S1
OPEN
GND
VCC
Note : 1. CL includes probe and jig capacitance.
REJ03D0619-0300 Rev.3.00 Mar 25, 2009
Page 5 of 9
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HD74HC373.PDF ] | |
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