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PDF R1EX25064ATA00A Data sheet ( Hoja de datos )
| Número de pieza | R1EX25064ATA00A | |
| Descripción | EEPROM | |
| Fabricantes | Renesas | |
| Logotipo |  |
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R1EX25032ASA00A/R1EX25064ASA00A
R1EX25032ATA00A/R1EX25064ATA00A
Serial Peripheral Interface
32k EEPROM (4-kword × 8-bit)
64k EEPROM (8-kword × 8-bit)
Electrically Erasable and Programmable Read Only Memory
REJ03C0358-0002
Preliminary
Rev.0.02
Jan.14.2009
Description
R1EX25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 32-byte
page programming function to make it’s write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phones,
camcorders, audio equipments. Therefore, please contact Renesas Technology’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
• Single supply: 1.8 V to 5.5 V
• Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
• Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
• Power dissipation:
Standby: 2µA (max)
Active (Read): 3.0 mA (max)
Active (Write): 3.5 mA (max)
• Automatic page write: 32-byte/page
• Write cycle time: 5 ms
• Endurance: 1,000k Cycles @25°C
• Data retention: 100 Years @25°C
• Small size packages: SOP-8pin, TSSOP-8pin
• Shipping tape and reel
TSSOP-8pin : 3,000 IC/reel
SOP-8pin : 2,500 IC/reel
• Temperature range: −40 to +85°C
• Lead free product.
REJ03C0358-0002.Rev.0.02 Jan.14.2009
page 1 of 20
1 page  
R1EX25032Axx00A/R1EX25064Axx00A
AC Characteristics
Test Conditions
• Input pules levels:
VIL = VCC × 0.2
VIH = VCC × 0.8
• Input rise and fall time: ≤ 10 ns
• Input and output timing reference levels: VCC × 0.3, VCC × 0.7
• Output reference levels: VCC × 0.5
• Output load: 100 pF
Parameter
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock high setup time before HOLD active
Clock high setup time before HOLD not
active
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output low-Z
HOLD low to output high-Z
Write time
Notes: 1. tCH + tCL ≥ 1/fC
2. Not 100% tested.
Symbol
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
tCHHH
tSHQZ
tCLQV
tCLQX
tQLQH
tQHQL
tHHQX
tHLQZ
tW
Alt
fSCK
tCSS1
tCSS2
tCS
tCSH
tCLH
tCLL
tRC
tFC
tDSU
tDH
tDIS
tV
tHO
tRO
tFO
tLZ
tHZ
tWC
(Ta = −40 to +85°C, VCC = 2.5 V to 5.5 V)
Min Max Unit Notes
5 MHz
90 ns
90 ns
90 ns
90 ns
90 ns
90 ns
1
90 ns
1
1 µs 2
1 µs 2
20 ns
30 ns
70 ns
40 ns
60 ns
60 ns
100 ns
70 ns
0 ns
50 ns
50 ns
50 ns
100 ns
5 ms
2
2
2
2
2
REJ03C0358-0002.Rev.0.02 Jan.14.2009
page 5 of 20
5 Page 
R1EX25032Axx00A/R1EX25064Axx00A
Write Disable (WRDI):
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown
in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction
byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The
Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Write Disable (WRDI) Sequence
VIH
S
VIL
VIH
W
VIL
VIH
C
VIL
VIH
D
VIL
0 1 2 345 6 7
Instruction
Q High-Z
REJ03C0358-0002.Rev.0.02 Jan.14.2009
page 11 of 20
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet R1EX25064ATA00A.PDF ] | |
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