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PDF LTC6820 Data sheet ( Hoja de datos )
| Número de pieza | LTC6820 | |
| Descripción | isoSPI Isolated Communications Interface | |
| Fabricantes | Linear | |
| Logotipo |  |
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LTC6820
isoSPI Isolated
Communications Interface
Features
Description
n 1Mbps Isolated SPI Data Communications
n Simple Galvanic Isolation Using Standard
Transformers
n Bidirectional Interface Over a Single Twisted Pair
n Supports Cable Lengths Up to 100 Meters
n Very Low EMI Susceptibility and Emissions
n Configurable for High Noise Immunity or Low Power
n Engineered for ISO26262 Compliant Systems
n Requires No Software Changes in Most SPI Systems
n Ultralow, 2µA Idle Current
n Automatic Wake-Up Detection
n Operating Temperature Range: –40°C to 125°C
n 2.7V to 5.5V Power Supply
n Interfaces to All Logic from 1.7V to 5.5V
n Available in 16-Lead QFN and MSOP Packages
Applications
n Industrial Networking
n Battery Monitoring Systems
n Remote Sensors
The LTC®6820 provides bidirectional SPI communications
between two isolated devices through a single twisted-
pair connection. Each LTC6820 encodes logic states into
signals that are transmitted across an isolation barrier to
another LTC6820. The receiving LTC6820 decodes the
transmission and drives the slave bus to the appropriate
logic states. The isolation barrier can be bridged by a simple
pulse transformer to achieve hundreds of volts of isolation.
The LTC6820 drives differential signals using matched
source and sink currents, eliminating the requirement
for a transformer center tap and reducing EMI. Precision
window comparators in the receiver detect the differential
signals. The drive currents and the comparator thresholds
are set by a simple external resistor divider, allowing the
system to be optimized for required cable lengths and
desired signal-to-noise performance.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and isoSPI
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Patents pending.
Typical Application
Microcontroller to SPI Slave Isolated Interface
MASTER
µC
SDO
SDI
SCK
CS
LTC6820
MSTR
MOSI IP
MISO
SCK IM
CS
120Ω
REMOTE
SLAVE IC
SDI
SDO
SCK
CS
LTC6820
MSTR
IP
MOSI
MISO
SCK IM
CS
100 METERS
TWISTED PAIR
120Ω
6820 TA01a
Data Rate vs Cable Length
1.2
CAT-5 ASSUMED
1.0
0.8
0.6
0.4
0.2
0
1 10 100
CABLE LENGTH (METERS)
6820 TA01b
For more information www.linear.com/LTC6820
6820fa
1
1 page  
Electrical Characteristics
of the time if MSTR = 0. See Applications Information section for more
detailed information.
Note 5: The IO supply pin, VDDS, provides power for the SPI inputs and
outputs, including the EN pin. If the inputs are near 0V or VDDS (to avoid
static current in input buffers) and the outputs are not sourcing current,
then IDDS includes only leakage current.
Note 6: The LTC6820 is guaranteed to meet specifications with RBIAS
resistor values ranging from 2k to 20k, with 1% or better tolerance. Those
resistor values correspond to a typical IB that can range from 0.1mA
(for 20k) to 1mA (for 2k).
Note 7: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
LTC6820
corresponds to 10m of CAT-5 cable (which has a velocity of propagation
of 66% the speed of light). Use of longer cables would require derating
these specs by the amount of additional delay.
Note 8: These specifications do not include rise or fall time. While fall
time (typically 5ns due to the internal pull-down transistor) is not a
concern, rising-edge transition time tRISE is dependent on the pull-up
resistance and load capacitance. In particular, t12 and t14 require tRISE
< 110ns (if SLOW = 0) for the slave’s setup and hold times. Therefore,
the recommended time constant is 50ns or less. For example, if the
total capacitance on the data pin is 25pF (including self capacitance
CI/O of 10pF), the required pull-up resistor value is RPU ≤ 2kΩ. If these
requirements can’t be met, use SLOW = 1.
Note 9: Guaranteed by design. Not tested in production.
Typical Performance Characteristics VDD = VDDS, unless otherwise noted.
Supply Current (READY/ACTIVE)
vs Clock Frequency
7
6 VDD = 5V, IB = 1mA
5
VDD = 3V, IB = 1mA
4
3 VDD = 5V, IB = 0.1mA
2
MSTR = 1
1
0 200
VDD = 3V, IB = 0.1mA
400 600 800
FREQUENCY (kHz)
1000
6820 G01
Supply Current (IDLE)
vs Supply Voltage
3.0
2.5
2.0 SLAVE (MSTR = 0)
1.5
1.0 MASTER (MSTR = 1)
0.5
0
2.5 3.0 3.5
4.0 4.5
5.0 5.5
SUPPLY VOLTAGE (V)
6820 G04
Supply Current (READY)
vs Temperature
5.3 IB = 1mA
5.2
VDD = 5V
5.1
VDD = 3V
5.0
4.9
4.8
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
6820 G02
Supply Current (IDLE)
vs Temperature
3.0
VDD = 5V
2.5
2.0
SLAVE (MSTR = 0)
1.5
1.0
MASTER (MSTR = 1)
0.5
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
6820 G05
For more information www.linear.com/LTC6820
Input Voltage Threshold
(Except EN Pin)
vs Supply Voltage (VDD or VDDS)
4.0
3.5
ONLY
3.0 SPI PINS
2.5
2.0
VIH
HIGH
LOW
1.5
1.0
VIL
0.5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
6820 G03
Output Resistance vs Supply
Voltage (VOH/VOL)
100
80
OUTPUT
SOURCING 2mA CURRENT
60
40
20
0
1.5
OUTPUT SINKING 3.3mA CURRENT
2.5 3.5 4.5
SUPPLY VOLTAGE (V)
5.5
6820 G19
6820fa
5
5 Page 
LTC6820
Operation
On the other side of the isolation barrier (i.e., the other end
of the cable) another LTC6820 is configured to interface
with a SPI slave. It receives the transmitted pulses and
reconstructs the SPI signals on its output port, as shown
in Table 3. In addition, the slave device may transmit a
return data pulse to the master to set the state of MISO.
See isoSPI Interaction and Timing for additional details.
Table 3. Slave SPI Port Output
RECEIVED PULSE SPI PORT ACTION
Long +1
Drive CS High
Long –1
Drive CS Low
Short +1
1. Set MOSI = 1
2. Pulse SCK
Short –1
1. Set MOSI = 0
2. Pulse SCK
RETURN PULSE
None
Short –1 Pulse
if MISO = 0
(No Return Pulse
if MISO = 1)
A slave LTC6820 never transmits long (CS) pulses. Fur-
thermore, a slave will only transmit a short –1 pulse (when
MISO = 0), never a +1 pulse. This allows for multiple slave
devices on a single cable without risk of collisions (see
Multidrop section).
isoSPI Pulse Specifications
Figure 2 details the timing specifications for the +1 and
–1 isoSPI pulses. The same timing specifications apply to
either version of these symmetric pulses. In the Electrical
Characteristics table, these specifications are further
separated into CS (long) and Data (short) parameters.
A valid pulse must meet the minimum spec for t1/2PW and
the maximum spec for tINV. In other words, the half-pulse
width must be long enough to pass through the appropriate
pulse timer, but short enough for the inversion to begin
within the valid window of time.
The response observed at MOSI, MISO or CS will occur
after delay tDEL from the pulse inversion.
Setting Clock Phase and Polarity (PHA and POL)
SPI devices often use one clock edge to latch data and
the other edge to shift data. This avoids timing problems
associated with clock skew. There is no standard to specify
whether the shift or latch occurs first. There is also no
requirement for data to be latched on a rising or falling
clock edge, although latching on the rising edge is most
common. The LTC6820 supports all four SPI operating
modes, as configured by the PHA and POL Pins.
Table 4. SPI Modes
MODE POL PHA
000
101
210
311
DESCRIPTION
SCK Idles Low, Latches on Rising (1st) Edge
SCK Idles Low, Latches on Falling (2nd) Edge
SCK Idles High, Latches on Falling (1st) Edge
SCK Idles High, Latches on Rising (2nd) Edge
+1 PULSE
VA
VTCMP
VIP – VIM
–VTCMP
–VA
MOSI, MISO OR CS
–1 PULSE
VA
VTCMP
VIP – VIM
–VTCMP
–VA
MOSI, MISO OR CS
t1/2PW
tINV
tINV
t1/2PW
t1/2PW
tDEL
t1/2PW
tDEL
Figure 2. isoSPI Differential Pulse Detail
For more information www.linear.com/LTC6820
6820 F02
6820fa
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC6820.PDF ] | |
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