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PDF K4W2G1646C Data sheet ( Hoja de datos )
| Número de pieza | K4W2G1646C | |
| Descripción | 2Gb gDDR3 SDRAM C-die | |
| Fabricantes | Samsung | |
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Rev. 1.1, Sep. 2010
K4W2G1646C
2Gb gDDR3 SDRAM C-die
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
1 page  
K4W2G1646C
datasheet
Rev. 1.1
gDDR3 SDRAM
17.13.5. tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .................................................................................. 95
17.13.6. tRPRE Calculation ....................................................................................................................................... 96
17.13.7. tRPST Calculation........................................................................................................................................ 96
17.13.8. Burst Read Operation followed by a Precharge........................................................................................... 102
17.14 WRITE Operation ................................................................................................................................................ 103
17.14.1. gDDR3 Burst Operation ............................................................................................................................... 103
17.14.2. WRITE Timing Violations ............................................................................................................................. 103
17.14.3. Motivation..................................................................................................................................................... 103
17.14.4. Data Setup and Hold Violations ................................................................................................................... 103
17.14.5. Strobe to Strobe and Strobe to Clock Violations.......................................................................................... 103
17.14.6. Write Timing Parameters ............................................................................................................................. 103
17.14.7. Write Data Mask........................................................................................................................................... 104
17.14.8. tWPRE Calculation....................................................................................................................................... 105
17.14.9. tWPST Calculation ....................................................................................................................................... 105
17.15 Refresh Command .............................................................................................................................................. 111
17.16 Self-Refresh Operation........................................................................................................................................ 112
17.17 Power-Down Modes ............................................................................................................................................ 113
17.17.1. Power-Down Entry and Exit ......................................................................................................................... 113
17.17.2. Power-Down clarifications - Case 1 ............................................................................................................. 117
17.17.3. Power-Down clarifications - Case 2 ............................................................................................................. 117
17.17.4. Power-Down clarifications - Case 3 ............................................................................................................. 118
17.18 ZQ Calibration Commands .................................................................................................................................. 119
17.18.1. Calibration Description ................................................................................................................................. 119
17.18.2. ZQ Calibration Timing .................................................................................................................................. 119
17.18.3. ZQ External Resistor Value and Tolerance and Capacitive loading ............................................................ 119
18. On-Die Termination (ODT).......................................................................................................................................... 120
18.1 ODT Mode Register and ODT Truth Table............................................................................................................ 120
18.2 Synchronous ODT Mode ....................................................................................................................................... 121
18.2.1. ODT Latency and Posted ODT ...................................................................................................................... 121
18.2.2. Timing Parameters......................................................................................................................................... 121
18.2.3. ODT during Reads: ........................................................................................................................................ 123
18.3 Dynamic ODT ........................................................................................................................................................ 124
18.3.1. Functional Description:................................................................................................................................... 124
18.3.2. ODT Timing Diagrams ................................................................................................................................... 125
18.4 Asynchronous ODT mode ..................................................................................................................................... 127
18.4.1. Synchronous to Asynchronous ODT Mode Transition ................................................................................... 127
18.4.2. Synchronous to Asynchronous ODT Mode Transition during Powerdown Entry........................................... 128
18.4.3. Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit ........................................... 130
18.4.4. Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods .................... 131
-5-
5 Page 
K4W2G1646C
datasheet
Rev. 1.1
gDDR3 SDRAM
6. Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
[ Table 4 ] Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
NOTE
VDD
VDDQ
VIN, VOUT
TSTG
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
V 1,3
V 1,3
V1
°C 1, 2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be
equal to or less than 300mV.
6.2 DRAM Component Operating Temperature Range
[ Table 5 ] Temperature Range
Symbol
Parameter
rating
Unit NOTE
TOPER
Operating Temperature Range
0 to 95
°C 1, 2, 3
NOTE :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
7. AC & DC Operating Conditions
7.1 Recommended DC operating Conditions (SSTL_1.5)
[ Table 6 ] Recommended DC Operating Conditions
Symbol
Parameter
Min.
VDD Supply Voltage
1.425
VDDQ
Supply Voltage for Output
1.425
NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Rating
Typ.
1.5
1.5
Max.
1.575
1.575
Units
V
V
NOTE
1,2
1,2
- 11 -
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