|
|
PDF LAN9500 Data sheet ( Hoja de datos )
| Número de pieza | LAN9500 | |
| Descripción | USB 2.0 to 10/100 Ethernet Controller | |
| Fabricantes | Microchip | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LAN9500 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
LAN9500/LAN9500i/LAN9500A/LAN9500Ai
LAN950x USB 2.0 to 10/100 Ethernet Controller
Highlights
• Single Chip Hi-Speed USB 2.0 to 10/100 Ethernet
Controller
• Integrated 10/100 Ethernet MAC with Full-Duplex
Support
• Integrated 10/100 Ethernet PHY with HP Auto-
MDIX support
• Integrated USB 2.0 Hi-Speed Device Controller
• Integrated USB 2.0 Hi-Speed PHY
• Implements Reduced Power Operating Modes
Target Applications
• Embedded Systems
• Set-Top Boxes
• PVRs
• CE Devices
• Networked Printers
• USB Port Replicators
• Standalone USB to Ethernet Dongles
• Test Instrumentation
• Industrial
Key Features
• USB Device Controller
- Fully compliant with Hi-Speed Universal
Serial Bus Specification Revision 2.0
- Supports HS (480 Mbps) and FS (12 Mbps)
modes
- Four endpoints supported
- Supports vendor specific commands
- Integrated USB 2.0 PHY
- Remote wakeup supported
• High-Performance 10/100 Ethernet Controller
- Fully compliant with IEEE802.3/802.3u
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and half-duplex support
- Full- and half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and check-
ing
- Automatic payload padding and pad removal
- Loop-back modes
- TCP/UDP/IP/ICMP checksum offload support
2010 - 2015 Microchip Technology Inc.
- Flexible address filtering modes
–One 48-bit perfect address
–64 hash-filtered multicast addresses
–Pass all multicast
–Promiscuous mode
–Inverse filtering
–Pass all incoming with status report
- Wakeup packet support
- Integrated Ethernet PHY
–Auto-negotiation
–Automatic polarity detection and correction
–HP Auto-MDIX support
–Link status change wake-up detection
- Support for 3 status LEDs
- External MII and Turbo MII support Home-
PNA™ and HomePlug® PHY
• Power and I/Os
- Various low power modes
- NetDetach feature increases battery life1
- Supports PCI-like PME wake1
- 11 GPIOs
- Supports bus-powered and self-powered
operation
- Integrated power-on reset circuit
- Single external 3.3v I/O supply
–Internal core regulator
• Miscellaneous Features
- EEPROM Controller
- Supports custom operation without
EEPROM1
- IEEE 1149.1 (JTAG) Boundary Scan
- Requires single 25 MHz crystal
• Software
- Windows XP/Vista Driver
- Linux Driver
- Win CE Driver
- MAC OS Driver
- EEPROM Utility
• Packaging
- 56-pin QFN (8x8 mm) RoHS Compliant
Environmental
- Commercial Temperature Range (0°C to
+70°C)
- Industrial Temperature Range (-40°C to
+85°C)
1 = LAN9500A/LAN9500Ai ONLY
DS00001875A-page 1
1 page  
LAN950x
FIGURE 1-1:
SYSTEM COMPONENT DIFFERENCES
LAN950x
56-PIN QFN TXP
TXN
+3.3V
Analog
49.9
Ohm
1%
49.9
Ohm
1%
49.9
Ohm
1%
49.9
Ohm
1%
R1
For LAN9500/LAN9500i: 10 Ohm 1%
For LAN9500A/LAN9500Ai: 0 Ohm
Ethernet Magnetics/RJ45
RXP
RXN
To
Ethernet
EXRES
R2
XO
R3
XI
25.000MHz
For LAN9500/LAN9500i: 12.4K Ohm 1%
For LAN9500A/LAN9500Ai: 12.0K Ohm 1%
For LAN9500/LAN9500i: 1M Ohm 1%
For LAN9500A/LAN9500Ai: Do Not Populate
33pF 33pF
2010 - 2015 Microchip Technology Inc.
DS00001875A-page 5
5 Page 
3.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 3-1:
PIN ASSIGNMENTS (TOP VIEW)
LAN950x
TXEN 43
RXER 44
CRS/GPIO3 45
COL/GPIO0 *** 46
TXCLK 47
VDD33IO 48
TEST1 49
VDDCORE 50
VDD33IO 51
VDD33IO 52
TXD3/GPIO7/EEP_SIZE **** 53
TXD2/GPIO6/PORT_SWAP 54
TXD1/GPIO5/RMT_WKP 55
TXD0/GPIO4/EEP_DISABLE 56
LAN950x
56 PIN QFN
(TOP VIEW)
VSS
28 nSPD_LED/GPIO10 ***
27 nLNKA_LED/GPIO9 ***
26 nFDX_LED/GPIO8 ***
25 VDD33IO
24 nRESET ***
23 MDIO/GPIO1 ***
22 MDC/GPIO2
21 VDDCORE
20 VBUS_DET ***
19 XO
18 XI
17 VDDUSBPLL
16 USBRBIAS
15 VDD33A
Note 1: ** This pin is a no-connect (NC) for LAN9500A/LAN9500Ai, but may be connected to VDD33A for backward
compatibility with LAN9500/LAN9500i.
2: *** For LAN9500A/LAN9500Ai this pin provides additional PME related functionality. Refer to the respective
pin descriptions and Section 6.0, "PME Operation," on page 112 for additional information.
3: **** For LAN9500A/LAN9500Ai GPIO7 may provide additional PHY Link Up related functionality. Refer to
Section 5.12.2.4, "Enabling PHY Link Up Wake Events (LAN9500A/LAN9500Ai ONLY)," on page 108 for
additional information.
4: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa.
5: Exposed pad (VSS) on bottom of package must be connected to ground.
2010 - 2015 Microchip Technology Inc.
DS00001875A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN9500.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LAN9500 | USB 2.0 to 10/100 Ethernet Controller | Microchip |
| LAN9500A | USB 2.0 to 10/100 Ethernet Controller | Microchip |
| LAN9500Ai | USB 2.0 to 10/100 Ethernet Controller | Microchip |
| LAN9500i | USB 2.0 to 10/100 Ethernet Controller | Microchip |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |