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PDF LAN8820 Data sheet ( Hoja de datos )
| Número de pieza | LAN8820 | |
| Descripción | RGMII 10/100/1000 Ethernet Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN8820 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN8820/LAN8820I
RGMII 10/100/1000 Ethernet Transceiver
with HP Auto-MDIX Support
Highlights
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• Compliant with IEEE 802.3ab (1000BASE-T),
IEEE 802.3u (Fast Ethernet), and ISO 802-3/IEEE
802.3 (10BASE-T)
• HP Auto-MDIX support in accordance with IEEE
802.3ab specification at 10/100/1000 Mbps oper-
ation
• Miniature 56-pin QFN lead-free RoHS compliant
package with RGMII (8 x 8 x 0.85mm height)
• Flexible configurations for LED status indicators
• Implements Reduced Power Operating Modes
Target Applications
• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adaptors/Servers
• Gaming Consoles
• POE Applications
Key Benefits
• High-Performance 10/100/1000 Ethernet Trans-
ceiver
- Compliant with IEEE 802.3ab (1000BASE-T)
- Compliant with IEEE 802.3/802.3u (Fast
Ethernet)
- Compliant with ISO 802-3/IEEE 802.3
(10BASE-T)
- 10BASE-T, 100BASE-TX and 1000BASE-T
support
- Loop-back modes
- Auto-negotiation (NEXT page support)
- Automatic polarity detection and correction
- Link status change wake-up detection
- Vendor specific register functions
- Supports reduced pin count RGMII interface
- Controlled impedance outputs
- Supports RGMII ID mode
- Four status LED outputs and configurable
LED modes with support for tricolor operation
- Compliant with IEEE 802.3-2005 standards
- RGMII pins tolerant to 3.6V
- Integrated DSP implements adaptive equal-
izer, echo cancellers, and crosstalk cancel-
lers
- Efficient digital baseline wander correction
• Power and I/Os
- Configurable LED outputs
- Various low power modes
- 2.5V I/O supply
• Miscellaneous Features
- IEEE 1149.1 (JTAG) boundary scan
- Multiple clock options - 25MHz crystal or
25MHz single-ended clock
• Packaging
- 56-pin QFN (8x8 mm) RoHS compliant pack-
age with RGMII
• Environmental
- Commercial temperature range
(0°C to +70°C)
- Industrial temperature range (-40°C to
+85°C)
2009-2015 Microchip Technology Inc.
DS00001871B-page 1
1 page  
LAN8820/LAN8820I
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
56-QFN PIN ASSIGNMENTS (TOP VIEW)
TR0N 43
TR0P 44
VDD12A 45
TR1N 46
TR1P 47
VDD12A 48
VDD12BIAS 49
VDD12PLL 50
TR2N 51
TR2P 52
VDD12A 53
TR3N 54
TR3P 55
VDD12A 56
LAN8820/LAN8820i
56 PIN QFN
(TOP VIEW)
VSS
28 TXCTRL
27 TXD0
26 TXD1
25 TXD2
24 VDD25IO
23 VDD12CORE
22 TXD3
21 NC
20 VDD12CORE
19 VDD25IO
18 RXC
17 IRQ
16 nRESET
15 HPD
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
2009-2015 Microchip Technology Inc.
DS00001871B-page 5
5 Page 
LAN8820/LAN8820I
TABLE 2-8: 56-QFN PIN ASSIGNMENTS
Pin
Num
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
TDI
TCK
TMS
TDO
XI
XO
VDD25IO
VDD12CORE
RXD0
RXD1
RXD2
RXD3
VDD12CORE
RXCTRL
Pin
Num
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
Pin
Num
Pin Name
HPD 29 TXC
nRESET
30 VDD12CORE
IRQ 31 1000_LED/
RGMII_ID_MODE
RXC
32 100_LED/
HPD_MODE
VDD25IO
33
10_LED
VDD12CORE
34
CONFIG3
NC 35 CONFIG2
TXD3
36 VDD12CORE
VDD12CORE
37
VDD25IO
VDD25IO 38 CONFIG1
TXD2
39 CONFIG0
TXD1 40 MDC
TXD0 41 MDIO
TXCTRL
42 ETHRBIAS
EXPOSED PAD
MUST BE CONNECTED TO VSS
Pin
Num
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pin Name
TR0N
TR0P
VDD12A
TR1N
TR1P
VDD12A
VDD12BIAS
VDD12PLL
TR2N
TR2P
VDD12A
TR3N
TR3P
VDD12A
2009-2015 Microchip Technology Inc.
DS00001871B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN8820.PDF ] | |
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