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PDF M24512-125 Data sheet ( Hoja de datos )
| Número de pieza | M24512-125 | |
| Descripción | Automotive 512-Kbit serial I2C bus EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M24512-125
Automotive 512-Kbit serial I²C bus EEPROM
Features
■ Compatible with all I2C bus modes:
– 400 kHz Fast mode
– 100 kHz Standard mode
■ Memory array:
– 512 Kbit (64 Kbytes) of EEPROM
– Page size: 128 bytes
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Single supply voltage: 2.5 V to 5.5 V
■ Operating temperature range: from -40 °C up
to +125 °C
■ Random and sequential Read modes
■ Write protect of the whole memory array
■ Enhanced ESD/Latch-Up protection
■ More than 1 million Write cycles
■ More than 40-year data retention
■ Packages
– RoHS compliant and halogen-free
(ECOPACK®)
Datasheet − production data
TSSOP8 (DW)
169 mil width
SO8 (MN)
150 mil width
March 2012
This is information on a product in full production.
Doc ID 022650 Rev 1
1/30
www.st.com
1
1 page  
M24512-125
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 26
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 27
Doc ID 022650 Rev 1
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5 Page 
M24512-125
Device operation
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
4.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier(1)
Chip Enable address(2)
b7 b6 b5 b4 b3 b2 b1
1 0 1 0 E2 E1 E0
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
RW
b0
RW
The device select code consists of a 4-bit device type identifier 1010b, and a 3-bit Chip
Enable address (E2, E1, E0). A device select code handling a value other than 1010b is not
acknowledged by the device.
Doc ID 022650 Rev 1
11/30
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