XC18V256 Datasheet PDF - Xilinx
| Part Number | XC18V256 | |
| Description | In-System Programmable Configuration PROMs | |
| Manufacturers | Xilinx | |
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— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
25
R
XC18V00 Series In-System-Programmable
Configuration PROMs
DS026 (v6.0) August 5, 2015
0
Features
• In-System Programmable 3.3V PROMs for
Configuration of Xilinx FPGAs
♦ Endurance of 20,000 Program/Erase Cycles
♦ Program/Erase Over Full Industrial Voltage and
Temperature Range (–40°C to +85°C)
• IEEE Std 1149.1 Boundary-Scan (JTAG) Support
• JTAG Command Initiation of Standard FPGA
Configuration
• Simple Interface to the FPGA
• Cascadable for Storing Longer or Multiple Bitstreams
Product Specification
• Low-Power Advanced CMOS FLASH Process
• Dual Configuration Modes
♦ Serial Slow/Fast Configuration (up to 33 MHz)
♦ Parallel (up to 264 Mb/s at 33 MHz)
• 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
• 3.3V or 2.5V Output Capability
• Design Support Using the Xilinx ISE™ Foundation™
Software Packages
• Available in PC20, SO20, PC44, and VQ44 Packages
• Lead-Free (Pb-Free) Packaging
Description
Xilinx introduces the XC18V00 series of in-system
programmable configuration PROMs (Figure 1). Devices in
this 3.3V family include a 4-megabit, a 2-megabit, a
1-megabit, and a 512-kilobit PROM that provide an easy-to-
use, cost-effective method for reprogramming and storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE and OE are enabled, data is available on the
PROM DATA (D0) pin that is connected to the FPGA DIN
pin. New data is available a short access time after each
rising clock edge. The FPGA generates the appropriate
number of clock pulses to complete the configuration. When
the FPGA is in Slave Serial mode, the PROM and the FPGA
are clocked by an external clock.
X-Ref Target - Figure 1
CLK CE
When the FPGA is in Master SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM. When
the FPGA is in Slave Parallel or Slave SelectMAP mode, an
external oscillator generates the configuration clock that
drives the PROM and the FPGA. After CE and OE are
enabled, data is available on the PROM’s DATA (D0-D7)
pins. New data is available a short access time after each
rising clock edge. The data is clocked into the FPGA on the
following rising edge of the CCLK. A free-running oscillator
can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output
to drive the CE input of the following device. The clock
inputs and the DATA outputs of all PROMs in this chain are
interconnected. All devices are compatible and can be
cascaded with other members of the family or with the
XC17V00 one-time programmable serial PROM family.
OE/RESET
TCK
Control
Data
Serial
CEO
TMS
TDI
and
JTAG
Address
Memory
Data
or
Parallel
D0 DATA
Serial or Parallel Mode
Interface
Interface
7 D[1:7]
TDO
Parallel Interface
CF
Figure 1: XC18V00 Series Block Diagram
DS026_01_040204
© 1999–2008, 2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries.
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
1
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— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
R XC18V00 Series In-System-Programmable Configuration PROMs
Xilinx FPGAs and Compatible PROMs
Table 2 provides a list of Xilinx FPGAs and compatible PROMs.
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00 Solution
XC2VP2
1,305,376
XC18V02
XC2VP4
3,006,496
XC18V04
XC2VP7
4,485,408
XC18V04 +
XC18V512
XC2VP20
8,214,560
2 of XC18V04
XC2VP30
11,589,920
3 of XC18V04
XC2VP40
15,868,192
4 of XC18V04
XC2VP50
19,021,344
5 of XC18V04
XC2VP70
26,098,976
6 of XC18V04 +
XC18V512
XC2VP100
34,292,768
8 of XC18V04 +
XC18V512
XC2V40
470,048
XC18V512
XC2V80
732,576
XC18V01
XC2V250
1,726,880
XC18V02
XC2V500
2,767,520
XC18V04
XC2V1000
4,089,504
XC18V04
XC2V1500
5,667,488
XC18V04
+ XC18V02
XC2V2000
7,501,472
2 of XC18V04
XC2V3000
10,505,120
3 of XC18V04
XC2V4000
15,673,248
4 of XC18V04
XC2V6000
21,865,376
5 of XC18V04 +
XC18V02
XC2V8000
29,081,504
7 of XC18V04
XCV50
559,200
XC18V01
XCV100
781,216
XC18V01
XCV150
1,040,096
XC18V01
XCV200
1,335,840
XC18V02
XCV300
1,751,808
XC18V02
XCV400
2,546,048
XC18V04
XCV600
3,607,968
XC18V04
XCV800
4,715,616
XC18V04 +
XC18V512
XCV1000
6,127,744
XC18V04 +
XC18V02
XCV50E
630,048
XC18V01
XCV100E
863,840
XC18V01
XCV200E
1,442,016
XC18V02
XCV300E
1,875,648
XC18V02
XCV400E
2,693,440
XC18V04
XCV405E
3,430,400
XC18V04
Table 2: Xilinx FPGAs and Compatible PROMs (Cont’d)
Device
Configuration
Bits
XC18V00 Solution
XCV600E
3,961,632
XC18V04
XCV812E
6,519,648
2 of XC18V04
XCV1000E
6,587,520
2 of XC18V04
XCV1600E
8,308,992
2 of XC18V04
XCV2000E
10,159,648
3 of XC18V04
XCV2600E
12,922,336
4 of XC18V04
XCV3200E
16,283,712
4 of XC18V04
XC2S15
197,696
XC18V512
XC2S30
336,768
XC18V512
XC2S50
559,200
XC18V01
XC2S100
781,216
XC18V01
XC2S150
1,040,096
XC18V01
XC2S200
1,335,840
XC18V02
XC2S50E
630,048
XC18V01
XC2S100E
863,840
XC18V01
XC2S150E
1,134,496
XC18V02
XC2S200E
1,442,016
XC18V02
XC2S300E
1,875,648
XC18V02
XC2S400E
2,693,440
XC18V04
XC2S600E
3,961,632
XC18V04
XC3S50
439,264
XC18V512
XC3S200
1,047,616
XC18V01
XC3S400
1,699,136
XC18V02
XC3S1000
3,223,488
XC18V04
XC3S1500
5,214,784
XC18V04 +
XC18V01
XC3S2000
7,673,024
2 of XC18V04
XC3S4000
11,316,864
3 of XC18V04
XC3S5000
13,271,936
3 of XC18V04 +
XC18V01
Capacity
Devices
XC18V04
XC18V02
XC18V01
XC18V512
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
5
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