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PDF ADP1053 Data sheet ( Hoja de datos )
| Número de pieza | ADP1053 | |
| Descripción | 3-Channel Digital Power Supply Controller | |
| Fabricantes | Analog Devices | |
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Data Sheet
3-Channel Digital
Power Supply Controller
ADP1053
FEATURES
Configurable 8-PWM engine with up to 3 channels
2 independent digitally controlled channel outputs
Voltage mode PWM control with 625 ps resolution
Remote voltage sensing on both channels
Programmable compensation filters
Voltage feedforward option
Flexible start-up sequencing and tracking
Switching frequency: 50 kHz to 625 kHz
Frequency synchronization
Independent channel protections: OVP and OCP
2 independent OTP circuits
Programmable fault protection sequence
Volt-second balance and dual-phase current balance
for interleaved configurations
On-board EEPROM
PMBus-compliant
Graphical user interface (GUI) for ease of programming
Available in a 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
AC-to-DC power supplies
Isolated dc-to-dc power supplies
Intermediate rail power supplies
Nonisolated dc-to-dc power converter
GENERAL DESCRIPTION
The ADP1053, based on a voltage mode PWM architecture, is
a flexible, application dedicated digital controller designed for
isolated and nonisolated dc-to-dc power supply applications.
The ADP1053 enables highly efficient power supply design and
facilitates the introduction of intelligent power management
techniques to improve energy efficiency at a system level.
The ADP1053 provides control, monitoring, and protection
of up to three independent channel outputs. The eight flexible
PWM outputs can be configured as three independent channels:
two regulated channels with feedback control plus one additional
unregulated channel with a fixed duty cycle. The frequency of
these three channels can be programmed individually from
50 kHz to 625 kHz; all channels can be synchronized internally
or to an external signal.
All eight PWM outputs can also be assigned to enable a single-
channel solution, which may be required in high power, high
efficiency applications.
Features include differential voltage sensing, fast current sensing,
flexible start-up sequencing and tracking, and synchronization
between devices to reduce low frequency system noise. Protection
and monitoring features include overcurrent protection (OCP),
undervoltage protection (UVP), overvoltage protection (OVP),
and overtemperature protection (OTP).
SIMPLIFIED TYPICAL APPLICATION CIRCUIT
VIN_DC
DRIVER
DRIVER
VOUT A+
DRIVER
RSENSE
LOAD
VOUT A–
PWM
OUTPUTS
ADP1053
CS2–_A
CS2+_A
VS+_A
iCoupler
VS–_A
DUPLICATE THE ABOVE SCHEMATICS FOR CHANNEL B
VOUT B+
VOUT B–
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
SPECIFICATIONS
VDD = 3.0 V to 3.6 V, TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range.
Table 1.
Parameter
SUPPLY
VDD
IDD
POWER-ON RESET
UVLO Threshold
VDD Rising
VDD Falling
OVLO Threshold
OVLO Debounce
VCORE PIN
Output Voltage
OSCILLATOR AND PLL
PLL Frequency
DPWM Resolution
VS_A, VS_B VOLTAGE SENSE
Input Voltage
Input Voltage FSR
VS_A, VS_B Accurate ADCs
Valid Input Voltage Range
ADC Register Update Rate
Resolution
Measurement Accuracy
Temperature Stability
Common-Mode Voltage Offset
VS_A, VS_B High Speed ADCs
Equivalent Resolution
Dynamic Range
VS_A, VS_B UVP
Threshold Accuracy
Comparator Update Speed
OVP_A, OVP_B PINS
Threshold Accuracy
Propagation Delay (Latency)
Test Conditions/Comments
PWM pins unloaded
Normal operation (PSON high)
Power supply off (PSON low)
Shutdown (VDD below UVLO)
During EEPROM programming
Min
3.0
When set to 2 μs
When set to 500 μs
2.750
3.7
330 nF capacitor between VCORE and
DGND
2.3
RES = 10 kΩ
Differential voltage from VS+_A to
VS−_A and from VS+_B to VS−_B
0
0
From 0% to 100% of valid input voltage
From 10% to 90% of valid input voltage
From 900 mV to 1.1 V
From 900 mV to 1.1 V
Voltage from VS−_A and VS−_B to AGND
to achieve measurement accuracy
−2.8
−44.8
−1.35
−21.6
−1.2
−19.2
−0.1
−200
At 390.6 kHz switching frequency
Regulation voltage 300 mV to 1.4 V
Based on VS_A, VS_B accurate ADC
Same as accurate ADC measurement
accuracy specifications
Debounce time not included
−1.7
Typ
3.3
30
30
100
IDD + 8
2.85
3.9
2
500
2.5
200
625
1
1.6
100
12
0
6
±10
10
58
ADP1053
Max
3.6
3.0
2.975
4.1
2.7
1.6
1.5
+2.1
+33.6
+2.1
+33.6
+1.65
+26.4
+0.1
+200
Unit
V
mA
mA
μA
mA
V
V
V
μs
μs
V
MHz
ps
V
V
V
Hz
Bits
% FSR
mV
% FSR
mV
% FSR
mV
mV/°C
mV
Bits
mV
ms
+1.6 %
110 ns
Rev. A | Page 5 of 84
5 Page 
Data Sheet
ADP1053
Pin No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
EP
Mnemonic
SDA
SCL
PSON_B
CS
CS1_B
PGOOD_B
CS2+_B
CS2−_B
OVP_B
PGND_B
VS−_B
VS+_B
FLGI/SYNI
FLGO/SYNO
RTD2
DGND
VCORE
VDD
AGND
RES
ADD
RTD1
Exposed Pad
Description
PMBus/I2C Serial Data Input and Output (Open-Drain). This signal is referenced to AGND.
PMBus/I2C Serial Clock Input and Output (Open-Drain). This signal is referenced to AGND.
Power Supply On Input for Channel B. This signal is referenced to DGND.
CS ADC Input and Fast Current Sense Input for Overcurrent Protection and Current Monitoring. This signal is
referenced to AGND.
CS1 ADC Input and Fast Current Sense Input for Channel B. This signal is referenced to AGND.
Power-Good Output (Open-Drain) for Channel B. This signal is referenced to AGND. This pin is controlled by the
PGOOD_B flag and is driven low when the flag is set. The PGOOD_B flag is set when the POWER_SUPPLY_B, UVP_B,
EEPROM_CRC, or SOFTSTART_FILTER_B flag is set. The ACSNS and OTW2 flags can also be programmed to be included.
Noninverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should
be 1 V for optimal operation.
Inverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should be 1 V
for optimal operation.
Overvoltage Protection Comparator Input for Channel B. This signal is referenced to PGND_B.
Reference Pin for Channel B Overvoltage Protection (OVP_B).
Inverting Input of the Voltage Sense ADC for Channel B Loop Control. There should be a low ohmic connection
to AGND.
Noninverting Input of the Voltage Sense ADC for Channel B Loop Control. This signal is referenced to VS−_B.
Flag Input/Synchronization Input. When this pin is programmed as a flag input, an external signal can be input
to generate a flag condition. The polarity is configurable. When this pin is programmed as a synchronization
input, the input signal is used as a reference for the internal PWM frequencies. This signal is referenced to AGND.
Flag Output/Synchronization Output. When this pin is programmed as a flag output, it can be used to indicate
the light load mode operation. The polarity is configurable. When this pin is programmed as a synchronization
output, it can be used as a frequency reference for synchronization. This signal is referenced to AGND.
Thermistor ADC Input from Zone 2. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed
from this pin to AGND. This signal is referenced to AGND.
IC Digital Ground. Reference ground for the digital circuitry of the ADP1053. This pin should be star-connected to
AGND.
Output of 2.5 V Regulator. Connect a 330 nF capacitor between this pin and DGND.
Positive Supply Voltage, 3.0 V to 3.6 V. This signal is referenced to AGND. Connect a 330 nF capacitor from VDD to
AGND.
IC Common Analog Ground. This pin should be star-connected to DGND.
Resistor Input. This pin sets the internal voltage reference for the ADP1053. Connect a 10 kΩ resistor (±1%) from
RES to AGND. This signal is referenced to AGND.
PMBus/I2C Address Select Input. Connect a resistor from ADD to AGND (see the PMBus/I2C Address section). This
signal is referenced to AGND.
Thermistor ADC Input from Zone 1. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed
from this pin to AGND. This signal is referenced to AGND.
The exposed pad on the underside of the package should be soldered to AGND.
Rev. A | Page 11 of 84
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP1053.PDF ] | |
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