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PDF EFM8SB1 Data sheet ( Hoja de datos )
| Número de pieza | EFM8SB1 | |
| Descripción | microcontrollers | |
| Fabricantes | Silicon Laboratories | |
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EFM8 Sleepy Bee Family
EFM8SB1 Data Sheet
The EFM8SB1, part of the Sleepy Bee family of MCUs, is the
world’s most energy friendly 8-bit microcontrollers with a compre-
hensive feature set in small packages.
These devices offer lowest power consumption by combining innovative low energy tech-
niques and short wakeup times from energy saving modes into small packages, making
them well-suited for any battery operated applications. With an efficient 8051 core, 14
high-quality capacitive sense channels, and precision analog, the EFM8SB1 family is al-
so optimal for embedded applications.
EFM8SB1 applications include the following:
• Touch pads / key pads
• Wearables
• Instrumentation panels
• Battery-operated consumer electronics
ENERGY FRIENDLY FEATURES
• Lowest MCU sleep current with supply
brownout (50 nA)
• Lowest MCU active current (150 μA / MHz
at 24.5 MHz)
• Lowest MCU wake on touch average
current (< 1 μA)
• Lowest sleep current using internal RTC
and supply brownout (< 300 nA)
• Ultra-fast wake up for digital and analog
peripherals (< 2 μs)
• Integrated LDO to maintain ultra-low active
current at all voltages
Core / Memory
CIP-51 8051 Core
(25 MHz)
Flash Program
Memory
(up to 8 KB)
RAM Memory
(up to 512 bytes)
Debug Interface
with C2
Clock Management
External
Oscillator
Low Power 20 MHz
RC Oscillator
Low Frequency
RC Oscillator
High Frequency
24.5 MHz RC
Oscillator
External 32 kHz RTC Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Brown-Out Detector
Serial Interfaces
UART
SPI
I2C / SMBus
I/O Ports
External
Interrupts
Pin Reset
General
Purpose I/O
Pin Wakeup
8-bit SFR bus
Timers and Triggers
Timers
0/1/2/3
PCA/PWM
Watchdog
Timer
Real Time
Clock
Analog Interfaces
ADC
Comparator 0
Internal Current Internal Voltage
Reference
Reference
Capacitive Sense
Security
16-bit CRC
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
Sleep
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2
1 page  
EFM8SB1 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Suspend
Stop
Sleep
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
• Core and digital peripherals halted
• Internal oscillators disabled
• Code resumes execution on wake event
• All internal power nets shut down
• Pins retain state
• Exit on any reset source
• Most internal power nets shut down
• Select circuits remain powered
• Pins retain state
• All RAM and SFRs retain state
• Code resumes execution on wake event
Mode Entry
—
Set IDLE bit in PCON0
Wake-Up Sources
—
Any interrupt
1. Switch SYSCLK to
HFOSC0 or LPOSC0
2. Set SUSPEND bit in
PMU0CF
• RTC0 Alarm Event
• RTC0 Fail Event
• CS0 Interrupt
• Port Match Event
• Comparator 0 Rising
Edge
Set STOP bit in PCON0 Any reset source
1. Disable unused ana-
log peripherals
2. Set SLEEP bit in
PMU0CF
• RTC0 Alarm Event
• RTC0 Fail Event
• Port Match Event
• Comparator 0 Rising
Edge
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7.
• Up to 17 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each pin.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 20 MHz low power oscillator divided by 8.
• Provides clock to core and peripherals.
• 20 MHz low power oscillator (LPOSC0), accurate to ±10% over supply and temperature corners.
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
• 16.4 kHz low-frequency oscillator (LFOSC0) or external RTC 32 kHz crystal.
• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK).
• Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 4
5 Page 
EFM8SB1 Data Sheet
System Overview
3.10 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in the last page of flash and can be erased if it is
not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the boot-
loader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The boot-
loader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
0xFFFF
Reserved
0x2000
0x1FFF
0x1FFE
0x1FFD
0x1E00
Lock Byte
Bootloader Signature Byte
Security Page
512 Bytes
Bootloader Vector
8 KB Flash
(16 x 512 Byte pages)
0x0000
Reset Vector
Figure 3.2. Flash Memory Map with Bootloader—8 kB Devices
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EFM8SB1.PDF ] | |
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