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PDF U74HC4046A Data sheet ( Hoja de datos )
| Número de pieza | U74HC4046A | |
| Descripción | PHASE LOCKED LOOP | |
| Fabricantes | Unisonic Technologies | |
| Logotipo |  |
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UNISONIC TECHNOLOGIES CO., LTD
U74HC4046A
PHASE LOCKED LOOP WITH VCO
CMOS IC
DESCRIPTION
The U74HC4046A is a phase-locked-loop circuit including a linear
voltage-controlled oscillator (VCO), three different phase comparators
(PC1, PC2 and PC3), a common signal input amplifier and a common
SOP-16
comparator input.
The signal can be directly coupled to large voltage signals or with a
series capacitor coupled to small voltage signals. Small voltage signals
can be kept within the linear region of the input amplifiers with a self-bias
input circuit. The U74HC4046A and a passive low-pass filter form a
second-order loop PLL. With a linear op-amp, the VCO achieves excellent
linearity.
The VCO requires an external capacitor and resistor. R1 (between R1
TSSOP-16
and GND) and capacitor C1 (between C1A and C1B) determine the
frequency range of the VCO. R2 (between R2 and GND) enables the
VCO to have a frequency offset if required.
For the high input impedance of the VCO, the design of low-pass filters is simplified, and the designer has a wide
choice of resistor/capacitor ranges. At pin 10 (DEMOUT), a demodulator output of the VCO input voltage is provided in
order not to load the low-pass filter. In conventional techniques, the DEMOUT voltage is one threshold voltage lower
than the VCO input voltage, but the DEMOUT voltage of U74HC4046 equals the VCO input voltage. When DEMOUT is
used, a load resistor (RS) should be connected from DEMOUT to GND; but if unused, DEMOUT should be left open.
The VCO output (VCOOUT) can be connected directly or via a frequency-divider to the comparator input (COMPIN). If
the VCO input is held at a constant DC level, the VCO output signal has a duty factor of 50% (maximum expected
deviation 1%). A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns
both off to minimize standby power consumption.
FEATURES
* Low Power Consumption
* Operating Power Supply Voltage Range: Digital Section 2.0 to 6.0 V
VCO Section 3.0 to 6.0 V
* Up to 17 MHz (typ.) Centre Frequency at VCC = 4.5 V
* Excellent VCO Frequency Linearity
* VCO-Inhibit Control For ON/OFF Keying and for Low Standby Power Consumption
* Minimal Frequency Drift
* Three Phase Comparators: EXCLUSIVE-OR;
Edge-Triggered JK Flip-Flop;
Edge-Triggered RS Flip-Flop
* Zero Voltage Offset due to OP-Amp Buffering
* Standard Output Capability
* MSI ICC Category
www.unisonic.com.tw
Copyright © 2013 Unisonic Technologies Co., Ltd
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1 page  
U74HC4046A
FUNCTIONAL DIAGRAM
CMOS IC
LOGIC DIAGRAM
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
5 of 19
QW-R502-461.C
5 Page 
U74HC4046A
CMOS IC
PHASE COMPARATORS (Cont.)
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detector. If the PLL is using the comparator, the loop is
controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 is
comprised of two D-type flip-flops, control-gating and a 3-state output stage. The circuit function is as an up-down
counter (Logic Diagram) for SIGIN causes an up-count and COMPIN causes a down-count.
The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is
VDEMOUT
=
V CC
4π
(φSIGIN
φ− COMPIN
)
where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter).
The phase comparator gain is:
KP
=
VCC
4π
(V/r
)
As shown in Fig.3, VDEMOUT is the resultant of the initial phase differences of SIGIN and COMPIN. Typical
waveforms for the PC2 loop locked at fo are shown in Fig.4.
4π
Fig.3 Phase comparator 2: average output voltage versus input phase difference.
Fig.4 Typical waveforms for PLL using phase comparator 2, loop locked at fo.
If the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type
output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). If the phase of
SIGIN lags that of COMPIN, the n-type driver is held “ON”.
If the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the
input signal cycle time, and for the remainder of the cycle both n and p-type drivers are “OFF” (3-state). If the
frequency of SIGIN is lower than that of COMPIN, the n-type driver that is held “ON” for most of the cycle. Then the
voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs
are equal in both phase and frequency. At this stable state the voltage on C2 remains constant as the PC2 output is
in 3-state and the VCO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator
pulse output (PCPOUT) is a HIGH level, and it indicates a locked condition.
For PC2, there is no phase difference between SIGIN and COMPIN over the full frequency range of the VCO.
And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are “OFF” for most of
the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the
capture range and this is independent of the low-pass filter. The VCO adjusts to its lowest frequency via PC2 when
no signal present at SIGIN.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
11 of 19
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