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PDF U74HCT7046 Data sheet ( Hoja de datos )
| Número de pieza | U74HCT7046 | |
| Descripción | PHASE LOCKED LOOP | |
| Fabricantes | Unisonic Technologies | |
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UNISONIC TECHNOLOGIES CO., LTD
U74HCT7046
PHASE LOCKED LOOP WITH VCO &
LOCK DETECTOR
CMOS IC
DESCRIPTION
The U74HCT7046 is phase-locked-loop circuit that comprise a linear
voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2),
a lock detector, a common signal input amplifier and a common
comparator input.
The lock detector capacitor should be connected between pin
15(CLD) and pin 8(GND).For a frequency range of 100kHz to 10MHz,the
lock detector capacitor must be 1000pF to 10pF,respectively.
The signal can be directly coupled to large voltage signals, or with a
series capacitor coupled to small signals. Small voltage signals can be
kept within the linear region of the input amplifiers with a self-bias input
circuit. The U74HCT7046 and a passive low-pass filter form a
second-order loop PLL. With a linear op-amp, the VCO achieves
excellent linearity.
The VCO requires external capacitor and resistor. R1 (between R1
and GND) and capacitor C1 (between C1A and C1B) determine the
frequency range of the VCO. R2 (between R2 and GND) enables the
VCO to have a frequency offset if required.
For the high input impedance of the VCO, the design of low-pass filters is simplified, and the designer has a wide
choice of resistor/capacitor ranges. At pin 10 (DEMOUT), a demodulator output of the VCO input voltage is provided
in order not to load the low-pass filter. In conventional techniques, the DEMOUT voltage is one threshold voltage
lower than the VCO input voltage, but the DEMOUT voltage of U74HCT7046 equals the VCO input voltage. When
DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; but if unused, DEMOUT should be
left open. The VCO output (VCOOUT) can be connected directly or via a frequency-divider to the comparator input
(COMPIN). If the VCO input is held at a constant DC level, the VCO output signal has a duty factor of 50%
(maximum expected deviation 1%). A LOW level at the inhibit input (INH) enables the VCO and demodulator, while
a HIGH level turns both off to minimize standby power consumption.
FEATURES
* Operating Power Supply Voltage Range: Digital Section 4.5 to 5.5 V
VCO Section 4.5 to 5.5 V
* Up to 18 MHz (typ.) Centre Frequency at VCC = 5V
* Excellent VCO Frequency Linearity
* VCO-Inhibit Control For ON/OFF Keying and for Low Standby Power Consumption
* Minimal Frequency Drift
* Zero Voltage Offset due to OP-Amp Buffering
www.unisonic.com.tw
Copyright © 2012 Unisonic Technologies Co., Ltd
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U74HCT7046
LOGIC DIAGRAM
CMOS IC
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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U74HCT7046
CMOS IC
PHASE COMPARATORS (Cont.)
If the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type
output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). If the phase of SIGIN
lags that of COMPIN, the n-type driver is held “ON”.
If the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the
input signal cycle time, and for the remainder of the cycle both n and p-type drivers are “OFF” (3-state). If the
frequency of SIGIN is lower than that of COMPIN, the n-type driver that is held “ON” for most of the cycle. Then the
voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs
are equal in both phase and frequency. At this stable state the voltage on C2 remains constant as the PC2 output is
in 3-state and the VCO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator
pulse output (PCPOUT) is a HIGH level, and it indicates a locked condition.
For PC2, there is no phase difference between SIGIN and COMPIN over the full frequency range of the VCO.
And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are “OFF” for most of
the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the
capture range and this is independent of the low-pass filter. The VCO adjusts to its lowest frequency via PC2 when
no signal present at SIGIN.
LOCK DETECTOR THEORY OF OPERATION
Detection of a locked condition is accomplished by a NOR gate and an envelope detector.When the PLL is in
Lock, the output of the NOR gate is High and the lock detector output (Pin 1) is at a constant high level. As the loop
tracks the signal on Pin 14 (signal in), the NOR gate outputs pulses whose widths represent the phase differ-ences
between the VCO and the input signal. The time between pulses will be approximately equal to the time constant of
the VCO center frequency. During the rise time of the pulse, the diode across the 1.5kΩ resistor is forward biased
and the time constant in the path that charges the lock detector capacitor is T = (150Ω x CLD).
During the fall time of the pulse the capacitor discharges through the 1.5kΩ and the 150Ω resistors and the
channel resistance of the n-device of the NOR gate to ground (T = (1.5kΩ + 150Ω + Rn-channel) x CLD).
The waveform preset at the capacitor resembles a sawtooth.The lock detector capacitor value is determined by
the VCO center frequency. The typical range of capacitor for a frequency of 10MHz is about 10pF and for a
frequency of 100kHz is about 1000pF. As long as the loop remains locked and tracking, the level of the sawtooth will
not go below the switching threshold of the Schmitt-trigger inverter. If the loop breaks lock, the width of the error
pulse will be wide enough to allow the sawtooth waveform to go below threshold and a level change at the output of
the Schmitt trigger will indicate a loss of lock. The lock detector capacitor also acts to filter out small glitches that can
occur when the loop is either seeking or losing lock.
FIGURE REFERENCES FOR DC CHARACTERISTICS
IIN
VIN
Self-Bias Operating Point
VIN
Fig.7 Typical input resistance curve at SIGIN, COMPIN.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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