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PDF 25L2026C Data sheet ( Hoja de datos )
| Número de pieza | 25L2026C | |
| Descripción | MX25L2026C | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX25L2026C
FEATURES
2M-BIT [x 1] CMOS SERIAL FLASH
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 2,097,152 x 1 bit structure
• 64 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 4 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 85MHz serial clock and 66MHz serial clock
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP4 status bits define the size of the area to be software protected against Program and Erase
instructions
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-pin SOP (150mil)
- All Pb-free devices are RoHS Compliant
P/N: PM1476
REV. 1.1, JUL. 21, 2009
1
1 page  
MX25L2026C
PROTECTED & UNPROTECTED
All of MX25L2026C protection bits, BP0~BP4, default is set to "1" (Protected) after Power-on and Erase/Program
process completion. MX25L2026C provides 2 kinds of unprotected methods, General Unprotection & Special
Unprotection.
Table 1.
Name
BP0
BP1
BP2
BP3
BP4
Status
Register
bit 2
bit 3
bit 4
bit 5
bit 6
Address Range
03F000h
03E000h
03C000h
03A000h
000000h
03FFFFh
03EFFFh
03DFFFh
03BFFFh
039FFFh
Note: BP0~BP4 Default set to "1", Protected.
Size
4KB
4KB
8KB
8KB
232KB
Method
General Unprotection
Special Unprotection
General Unprotection
General Unprotection is required on the range from address 03A000h to address 03FFFFh area unprotection,
BP0~BP3.
Firstly, SRWD status bit needs to individual set to 0. Then, set the protected bit to 0, BP0 or BP1 or BP2 or BP3,
which range needs to be Programmed/Erased. Finally, do the Program/Erase process.
Please refer to Flowchart 1.
Special Unprotection
Special Unprotection is required on the range from address 000000h to address 039FFFh area unprotection, BP4.
Firstly, SRWD status bit needs to individual set to 0. Then, it needs to write 4-command KEY to uplock BP4,
command C3/A5/C3/A5 sequence. This KEY command cannot insert any other command in this 4-command KEY
period. After KEY command pressed, set the protected bit BP4=0. Finally, do the Program/Erase command.
Please refer to Flowchart 2.
P/N: PM1476
REV. 1.1, JUL. 21, 2009
5
5 Page 
MX25L2026C
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 2.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction se-
quence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the
byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 2. Serial Modes Supported
CPOL CPHA
(Serial mode 0) 0
0 SCLK
shift in
(Serial mode 3) 1
1 SCLK
SI MSB
SO
shift out
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1476
REV. 1.1, JUL. 21, 2009
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25L2026C.PDF ] | |
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