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PDF PCU9661 Data sheet ( Hoja de datos )
| Número de pieza | PCU9661 | |
| Descripción | Parallel bus to 1 channel UFm I2C-bus controller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
Rev. 1 — 12 September 2011
Product data sheet
1. General description
The PCU9661 is an advanced single master mode I2C-bus controller. It is a fourth
generation bus controller designed for data intensive I2C-bus data transfers. It has a
transmit only transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus
with push-pull topology. The serial channel has a generous 4352 byte data buffer which
makes the PCU9661 the ideal companion to any CPU that needs to transmit and receive
large amounts of serial data with minimal interruptions.
The PCU9661 is an 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to
communicate with up to 64 slaves in one serial sequence with no intervention from the
CPU. The controller also has a sequence loop control feature that allows it to
automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.
Error reporting is handled at the transaction level, channel level, and controller level.
A simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are
referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
2. Features and benefits
Parallel-bus to I2C-bus protocol converter and interface
5 Mbit/s unidirectional data transfer Ultra Fast-mode (UFm) channel (push-pull driver)
Internal oscillator trimmed to 1 % accuracy reduces external components
4352-byte UFm channel buffer
Three levels of reset: software channel reset, global software reset on parallel bus,
global hardware RESET pin
Communicates with up to 64 slaves in one serial sequence
Sequence looping with interval timer
JTAG port available for boundary scan testing during board manufacturing process
Trigger input synchronizes serial communication exactly with external events
Maskable interrupts
Operating supply voltage: 3.0 V to 3.6 V (device and host interface)
1 page  
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
Table 2.
Symbol
TRST
TMS
TCK
TDI
TDO
INT
USDA2
USCL2
WR
RD
CE
TRIG
RESET
VDD(IO)
VSS(IO)
VDD
VSS
n.c.
Pin description …continued
Pin Type Description
13 I JTAG test reset input. For normal operation, hold LOW (VSS).
14 I JTAG test mode select input. For normal operation, hold HIGH
(VDD).
15 I JTAG test clock input. For normal operation, hold HIGH (VDD).
16 I JTAG test data in input. For normal operation, hold HIGH (VDD).
17 O JTAG test data out output. For normal operation, do not connect
(n.c.).
20 O Interrupt request: Active LOW, open-drain, output. This pin
requires a pull-up device.
21 O Channel 2 Ultra Fast-mode I2C-bus serial data output.
Push-pull drive. No pull-up device is needed.
22 O Channel 2 Ultra Fast-mode I2C-bus serial clock output.
Push-pull drive. No pull-up device is needed.
31 I Write strobe: When LOW and CE is also LOW, the content of the
data bus is loaded into the addressed register. Data are latched on
the rising edge of WR. CE may remain LOW or transition with WR.
32 I Read strobe: When LOW and CE is also LOW, causes the
contents of the addressed register to be presented on the data
bus. The read cycle begins on the falling edge of RD. Data lines
are driven when RD and CE are LOW. CE may transition with RD.
33 I Chip Enable: Active LOW input signal. When LOW, data transfers
between the host and the bus controller are enabled on D0 to D7
as controlled by the WR, RD and A0 to A7 inputs. When HIGH,
places the D0 to D7 lines in the 3-state condition.
During the initialization period, CE must transition with RD until
controller is ready.
34 I Trigger input: provides the trigger to start a new frame.
36 I Reset: Active LOW input. A LOW level resets the device to the
power-on state. Internally pulled HIGH through weak pull-up
current.
24 power I/O power supply: 3.0 V to 5.5 V. Power supply reference for
I2C-bus pins. Sets the voltage reference point for VIL/VIH and the
output drive rail for the UFm channel.
23 power
7, 18, 30, power
40, 44, 48
I/O supply ground. Can be tied to VSS.
Power supply: 3.0 V to 3.6 V. All VDD pins must be tied together
externally.
8, 19, 29, power Supply ground. All VSS pins must be tied together externally.
35, 39,
43, 47
25, 26,
27, 28
-
not connected
PCU9661
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2011
© NXP B.V. 2011. All rights reserved.
5 of 52
5 Page 
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
7.5.1.2 CONTROL — Control register
CONTROL is an 8-bit register. The STO bit is affected by the bus controller hardware: it is
cleared when a STOP condition is present on the I2C-bus.
Table 5. CONTROL - Control register bit description
Address: Channel 2 = E0h.
Legend: * reset value
Bit Symbol Access Value Description
7 STOSEQ R/W
Stop sequence bit.
1 When the STOSEQ bit is set while the channel is active, a
STOP condition will be transmitted immediately following
the end of the current sequence being transferred on the
I2C-bus. No further buffered transactions will be carried out
and the channel will return to the idle state. Normal error
reporting will occur up until the last bit. When a STOP
condition is detected on the bus, the hardware clears the
STOSEQ flag.
0* When STOSEQ is reset, no action will be taken.
6 STA
R/W
The START flag.
1 The STA bit is set to begin a sequence.
The STA bit may be set only at a valid idle state. The
controller will reset the bit under the following conditions:
• A sequence is done and FRAMECNT = 1.
• A sequence loop is done and FRAMECNT > 1.
• The STOSEQ bit is set, FRAMECNT = 0, and the
current sequence is done.
• The STOSEQ bit is set, FRAMECNT > 1, and the
current sequence is done.
• The STO bit is set and the current byte transaction is
done. This bit cannot be set if the CHEN bit is 0.
0* When the STA bit is reset, no START condition will be
generated.
5 STO
R/W
The STOP flag.
1 When the STO bit is set while the channel is active, a STOP
condition will be transmitted immediately following the
current data or slave address byte being transferred on the
I2C-bus. No further buffered transactions will be carried out
and the channel will return to the idle state. Normal error
reporting will occur up until the last bit.
When a STOP condition is detected on the bus, the
hardware clears the STO flag.
0* When the STO bit is reset, no action will be taken.
4 TP
R/W
Trigger polarity bit. Cannot be changed while channel is
active.
1 Trigger will be detected on a falling edge.
0* Trigger will be detected on a rising edge.
PCU9661
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2011
© NXP B.V. 2011. All rights reserved.
11 of 52
11 Page | ||
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