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PDF PCU9654 Data sheet ( Hoja de datos )

Número de pieza PCU9654
Descripción 8-bit UFm 5MHz I2C-bus 100mA 40V LED driver
Fabricantes NXP Semiconductors　
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCU9654 Hoja de datos, Descripción, Manual

PCU9654
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
Rev. 1 — 2 July 2012
Product data sheet
1. General description
The PCU9654 is a UFm I2C-bus controlled 8-bit LED driver optimized for voltage switch
dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output
has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that
operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the
LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps)
group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency
between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 %
to 99.6 % that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCU9654 operates with
a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow
voltages up to 40 V for LED supply.
The PCU9654 is one of the first LED controller devices in a new Ultra Fast-mode (UFm)
family. UFm devices offer higher frequency (up to 5 MHz).
The active LOW Output Enable input pin (OE) blinks all the LED outputs and can be used
to externally PWM the outputs, which is useful when multiple devices need to be dimmed
or blinked together without using software control.
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCU9654 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time, thus minimizing I2C-bus
commands. Six hardware address pins allow up to 64 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCU9654
through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set HIGH (LED off). This allows an easy and
quick way to reconfigure all device registers to the same condition.

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PCU9654 pdf
NXP Semiconductors
PCU9654
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
6. Pinning information
6.1 Pinning
VSS 1
A0 2
A1 3
A2 4
A3 5
A4 6
VSS 7
LED0 8
LED1 9
LED2 10
LED3 11
VSS 12
PCU9654PW
24 VDD
23 USDA
22 USCL
21 n.c.
20 A5
19 OE
18 VSS
17 LED7
16 LED6
15 LED5
14 LED4
13 VSS
002aag321
Fig 2. Pin configuration for TSSOP24
6.2 Pin description
Table 2.
Symbol
VSS
A0
A1
A2
A3
A4
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
OE
A5
n.c.
USCL
USDA
VDD
Pin description
Pin
1, 7, 12, 13, 18
2
3
4
5
6
8
9
10
11
14
15
16
17
19
20
21
22
23
24
Type
power supply
I
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I
power supply
Description
supply ground
address input 0
address input 1
address input 2
address input 3
address input 4
LED driver 0
LED driver 1
LED driver 2
LED driver 3
LED driver 4
LED driver 5
LED driver 6
LED driver 7
active LOW output enable for LEDs
address input 5
do not connect; reserved input
UFm serial clock line
UFm serial data line
supply voltage
PCU9654
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 36

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PCU9654 arduino
NXP Semiconductors
PCU9654
8-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
Table 6. MODE2 - Mode register 2 (address 01h) bit description …continued
Legend: * default value.
Bit Symbol Access
Value Description
2-
W
1* reserved; write must always be a logic 1[2]
1-
W
0* reserved; write must always be a logic 0[2]
0-
W
1* reserved; write must always be a logic 1[2]
[1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCU9654.
Applicable to registers from 02h (PWM0) to 0Dh (LEDOUT1) only.
[2] Remark: If you change these bits from their default values, the device will not perform as expected.
7.3.3 PWM0 to PWM7, individual brightness control
Table 7. PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value
Description
02h PWM0 7:0 IDC0[7:0] W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] W 0000 0000* PWM3 Individual Duty Cycle
06h PWM4 7:0 IDC4[7:0] W 0000 0000* PWM4 Individual Duty Cycle
07h PWM5 7:0 IDC5[7:0] W 0000 0000* PWM5 Individual Duty Cycle
08h PWM6 7:0 IDC6[7:0] W 0000 0000* PWM6 Individual Duty Cycle
09h PWM7 7:0 IDC7[7:0] W 0000 0000* PWM7 Individual Duty Cycle
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT1 registers).
duty cycle = I---D-----C----x-----7----:--0----
256
(1)
7.3.4 GRPPWM, group duty cycle control
Table 8. GRPPWM - Group brightness control register (address 0Ah) bit description
Legend: * default value
Address Register Bit Symbol Access Value
Description
0Ah GRPPWM 7:0 GDC[7:0] W
1111 1111* GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the eight outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT1
registers).
PCU9654
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 July 2012
© NXP B.V. 2012. All rights reserved.
11 of 36

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