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PDF F25L01PA Data sheet ( Hoja de datos )
| Número de pieza | F25L01PA | |
| Descripción | 3V Only 1 Mbit Serial Flash Memory | |
| Fabricantes | Elite Semiconductor | |
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ESMT
Flash
FEATURES
y Single supply voltage 2.7~3.6V
y Standard, Dual SPI
y Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 86MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz
(100MHz / 172MHz equivalent Dual SPI)
y Low power consumption
- Active current: 22 mA
- Standby current: 25 μ A
- Deep Power Down current: 10 μ A
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Page programming time: 1.5 ms (typical)
F25L01PA (2D)
3V Only 1 M bit Serial Flash Memory
with Dual Output
y Erase
- Chip erase time 1 sec (typical)
- Block erase time 0.75 sec (typical)
- Sector erase time 90 ms (typical)
y Page Programming
- 256 byte per programmable page
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L01PA –50PG2D
F25L01PA –86PG2D
F25L01PA –100PG2D
F25L01PA –50SG2D
F25L01PA –86SG2D
F25L01PA –100SG2D
Speed
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
Package
8-lead
SOIC
150 mil
8-pin
TSSOP
173 mil
(4.4mm)
Comments
Pb-free
Pb-free
GENERAL DESCRIPTION
The F25L01PA is a 1Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 512 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
is divided into 32 uniform sectors with 4K byte each; 2 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.2
1/31
1 page  
ESMT
F25L01PA (2D)
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Bit Name
Function
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 3)
3 BP1 Indicate current level of block write protection (See Table 3)
4 BP2 Indicate current level of block write protection (See Table 3)
5 TB Top / Bottom write protect
6 RESERVED Reserved for future use
7
BPL
1 = BP2,BP1,BP0 and TB are read-only bits
0 = BP2,BP1,BP0 and TB are read/writable
Note:
1. Only BP0, BP1, BP2, TB and BPL are writable.
2. BP0, BP1, BP2, TB and BPL are non-volatile.
Default at
Power-up
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
N/A
R/W
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
• Power-up
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write Status Register instructions
BUSY
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the Block-Protection (BP2,
BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1)
of the array as show in Table 3, The TB bit can be set with Write
Status Register (WRSR) instruction. The TB bit can not be written
to if the Block- Protection-Look (BPL) bit is 1 or WP is low.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.2
5/31
5 Page 
ESMT
F25L01PA (2D)
Fast Read Dual Output (50 MHz ~ 86 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on SI and SO pins. This allows data to be transferred from the
device at twice the rate of standard SPI devices. This instruction
is for quickly downloading code from Flash to RAM upon
power-up or for applications that cache code- segments to RAM
for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.2
11/31
11 Page | ||
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