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PDF FAN7391 Data sheet ( Hoja de datos )
| Número de pieza | FAN7391 | |
| Descripción | Gate-Drive IC | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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June 2014
FAN7391
High-Current, High & Low-Side, Gate-Drive IC
Features
Floating Channels for Bootstrap Operation to +600 V
Typically 4.5 A / 4.5 A Sourcing / Sinking Current
Driving Capability
Common-Mode dv/dt Noise-Canceling Circuit
Built-in Under-Voltage Lockout for Both Channels
Built-in Advanced Input Filter
Matched Propagation Delay for Both Channels
Logic (VSS) and Power (COM) Ground ±5 V Offset
3.3 V and 5 V Input Logic Compatible
Output In-Phase with Input
Applications
Plasma Display Panel (PDP) Sustain Driver
High-Intensity Discharge (HID) Lamp Ballast
Switching Mode Power Supply (SMPS)
Motor Driver
Related Resources
AN-6076 — Design and Application Guide of Boot-
strap Circuit for High-Voltage Gate-Drive IC
AN-9052 — Design Guide for Selection of Bootstrap
Components
AN-8102 — Recommendations to Avoid Short Pulse
Width Issues in HVIC Gate Driver Applications
Description
The FAN7391 is a monolithic high- and low-side gate-
drive IC, which can drive high-speed MOSFETs and
IGBTs that operate up to +600 V. It has a buffered output
stage with all NMOS transistors designed for high pulse
current driving capability and minimum cross-conduction.
Fairchild’s high-voltage process and common-mode
noise-canceling techniques provide stable operation of
the high-side driver under high-dv/dt noise circum-
stances. An advanced level-shift circuit offers high-side
gate driver operation up to VS=-9.8 V (typical) for
VBS=15 V.
The advanced input filter of HIN provides protection
against short-pulsed input signals caused by noise.
The UVLO circuit prevents malfunction when VDD and
VBS are lower than the specified threshold voltage.
The high-current and low-output voltage-drop feature
makes this device suitable for the PDP sustain pulse
driver, motor driver, switching mode power supply, and
high-power DC-DC converter applications.
14-SOP
Ordering Information
Part Number
FAN7391MX
Package
14-SOP
Operating Temperature Range
-40C ~ 125C
Packing Method
Tape & Reel
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
1 page  
Electrical Characteristics
VBIAS (VDD, VBS)=15.0 V, VS=VSS=COM, TA=25C, unless otherwise specified. The VIL, VIH, and IIN parameters are
referenced to VSS/COM and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are
referenced to COM and VS is applicable to the respective output signals HO and LO.
Symbol
Characteristics
Condition
Min. Typ. Max. Unit
POWER SUPPLY SECTION (VDD AND VBS)
VDDUV+ VDD and VBS Supply Under-Voltage
VBSUV+ Positive-Going Threshold
VDDUV- VDD and VBS Supply Under-Voltage
VBSUV- Negative-Going Threshold
VDDUVH VDD and VBS Supply Under-Voltage
VBSUVH Lockout Hysteresis Voltage
ILK Offset Supply Leakage Current
IQBS Quiescent VBS Supply Current
IQDD Quiescent VDD Supply Current
IPBS Operating VBS Supply Current
IPDD Operating VDD Supply Current
SHUNT REGULATOR SECTION
VSHUNT
VDDand VBS Shunt Regulator Clamping
Voltage
LOGIC INPUT SECTION (HIN, LIN)
8.0 8.8 9.8
7.4 8.3 9.0 V
VB=VS=600 V
VIN=0 V or 5 V
VIN=0 V or 5 V
fIN=20 kHz, rms value
fIN=20 kHz, rms value
0.5
50
45 80 µA
75 110
530 640
µA
530 640
VDD=Sweep or VBS=Sweep,
ISHUNT=5 mA
21
23
25 V
VIH Logic "1" Input Voltage
VIL Logic "0" Input Voltage
IIN+ Logic "1" Input Bias Current
IIN- Logic "0" Input Bias Current
RIN Input Pull-Down Resistance
GATE DRIVER OUTPUT SECTION (HO, LO)
VIN=5 V
VIN=0 V
2.5
V
1.2
25 50
µA
1.0 2.0
100 200
k
VOH High-Level Output Voltage, VBIAS-VO
No Load
VOL Low-Level Output Voltage, VO
No Load
IO+ Output High, Short-Circuit Pulsed Current(4) VO=0 V, VIN=5 V,PW<10 µs 3.5
IO- Output Low, Short-Circuit Pulsed Current(4) VO=15 V, VIN=0 V,PW<10 µs 3.5
VS
Allowable Negative VS Pin Voltage for HIN
Signal Propagation to HO
1.0 V
35 mV
4.5
A
4.5
-9.8 -7.0 V
VSS-
COM
VSS-COM/COM-VSS Voltage Endurability
-5 5 V
Note:
4. This parameter guaranteed by design.
Dynamic Electrical Characteristics
VBIAS (VDD, VBS)=15.0 V, VS=VSS=COM=0 V, CL=1000 pF, and TA=25C unless otherwise specified.
Symbol
Characteristics
Test Condition
Min. Typ.
ton Turn-On Propagation Delay
VS=0 V
toff Turn-Off Propagation Delay
VS=0 V
MT Delay Matching, HS & LS Turn-On/Off
150
150
15
tr Turn-On Rise Time
tf Turn-Off Fall Time
25
20
Max.
220
220
50
50
45
Unit
ns
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
5
www.fairchildsemi.com
5 Page 
Applications Information
1. Advanced Input Noise Filter
Figure 29 shows the input noise filter method, which has
symmetry duration between the input signal (tINPUT) and
the output signal (tOUTPUT) and helps to reject noise
spikes and short pulses. This input filter is applied to the
HIN. The upper pair of waveforms (Example A) shows
an input signal duration (tINPUT) much longer than input
filter time (tFLTHIN); it is approximately the same duration
between the input signal time (tINPUT) and the output
signal time (tOUTPUT). The lower pair of waveforms
(Example B) shows an input signal time (tINPUT) slightly
longer than input filter time (tFLTHIN); it is approximately
the same duration between input signal time (tINPUT) and
the output signal time (tOUTPUT).
HIN
t FLTHIN
t INPUT
tOUTPUT
HO
HIN
HO
t FLTHIN
tINPUT
tOUTPUT
Output duration is
same as input duration
Figure 29. Input Noise Filter Definition
2. Short-Pulsed Input Noise Rejection
Method
The Advanced input filter circuitry provides protection
against short-pulsed input signals caused by noise.
If the input signal duration is less than input filter time
(tFLTHIN), the output does not change states.
Example A and B of the Figure 30 show the input and
output waveforms with short-pulsed noise spikes with a
duration less than input filter time; the output does not
change states.
HIN
HO
(LOW)
tFLTHIN
t FLTHIN
t FLTHIN
HIN
tFLTHIN
t FLTHIN
t FLTHIN
HO
(HIGH)
Figure 30. Noise Rejecting Input Filter Definition
Figure 31 shows the characteristics of the input filters
while receiving narrow ON and OFF pulses. If input
signal pulse duration, PWHIN, is less than input filter
time, tFLTHIN; the output pulse, PWHO, is zero. The input
signal is rejected by input filter. Once the input signal
pulse duration, PWHIN, exceeds input filter time, tFLTHIN,
the output pulse durations, PWHO, matches the input
pulse durations, PWHIN. FAN7391 input filter time,
tFLTHIN, is about 50ns for the high-side outputs.
1000
900
Input Pulse
Output Pulse
800
700
600
500
400
300
200
100
0 100 200 300 400 500 600 700 800 900 1000
Input Pulse Width [ns]
Figure 31. Input Filter Characteristic of Narrow ON
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FAN7391.PDF ] | |
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