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PDF TDA21310 Data sheet ( Hoja de datos )
| Número de pieza | TDA21310 | |
| Descripción | High-Performance DrBLADE | |
| Fabricantes | Infineon | |
| Logotipo |  |
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High-Performance DrBLADE
5 mm x 5 mm x 0.6 mm IQFN
TDA21310
Data Sheet
Revision 2.1, 2013-09-05
Power Management and Multi Market
1 page  
3 Description
3.1 Pinout
TDA21310
Description
VIN Pin #9
VIN Pin #10
VIN Pin #11
VSWH Pin #12
PGND Pin #13
PGND Pin #14
PGND Pin #15
PGND Pin #16
VIN
VSWH
Pin #32 VCIN
Pin #31 VDRV
Pin #30 PGND
Pin #29 VSWH
Pin #28 VSWH
Pin #27 VSWH
Pin #26 VSWH
Pin #25 VSWH
Figure 2 Pinout, numbering and name of pins (transparent top view)
Table 2
I/O Signals
Pin No.
Name Pin Type Buffer Type Function
4
PWM I
+3.3 V logic PWM drive logic input
The tri-state PWM input is compatible with 3.3 V.
5
DR_EN I
+3.3 V logic Enable signal (active high)
Connect to GND to disable the IC.
6
BOOT I
Analog
Bootstrap voltage pin
Connect to BOOT capacitor
7
PHASE I
Analog
Switch node (reference for Boot voltage)
internally connected to VSWH pin, connect to BOOT
capacitor
12, 25 to 29, VSWH O
VSWH pad
Analog
Switch node output
High current output switching node
Data Sheet
5 Revision 2.1, 2013-09-05
5 Page 
TDA21310
Theory of Operation
Table 11 Timing Characteristics
Parameter
Symbol
Values
Unit Note / Test Condition
PWM tri-state to VSWH rising
delay or VSWH falling delay
VSWH Shutdown Hold-Off time
PWM to VSWH turn-off
propagation delay
PWM to VSWH turn-on
propagation delay
DR_EN turn-off propagation
delay falling
DR_EN turn-on propagation
delay rising
PWM minimum pulse width
PWM minimum off time
t_pts
t_tsshd
t_pdlu
t_pdll
t_pdl_DR_EN
t_pdh_DR_EN
ton_min_PWM
toff_min_PWM
Min.
–
–
–
–
–
–
–
–
Typ. Max.
15 – ns
150 –
20 –
20 –
20 –
20 –
25 –
100 –
5 Theory of Operation
The TDA21310 incorporates a high performance gate driver, one high-side power MOSFET and one low-side
power MOSFET in a single 32 pin LG-UIQFN-32-2 package. The advantages of this arrangement are found in
the areas of increased performance, increased efficiency and lower overall package and layout inductance. This
module is ideal for use in Synchronous Buck Regulators.
The power MOSFETs are optimized for 5 V gate drive enabling excellent high load and light load efficiency. The
gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to
+16 V. The power density for transmitted power in a multiphase regulator of this approach can easily be higher
than 40 W per phase within a 25 mm2 area.
5.1 Driver Characteristics
The gate driver of the TDA21310 has two input voltages, VCIN and VDRV. VCIN is the 5 V logic supply for the
driver. VDRV sets the driving voltage for the high side and low side MOSFETs. The reference for the gate driver
control circuit (VCIN) is CGND. To decouple the sensitive control circuitry (logic supply) from a noisy
environment a ceramic capacitor must be placed between VCIN and CGND close to the pins. VDRV needs also
to be decoupled using a ceramic capacitor (MLCC) between VDRV and PGND in close proximity to the pins.
PGND serves as reference for the power circuitry including the driver output stage.
Referring to the Block Diagram page 7, VCIN is internally connected to the UVLO circuit. It will force shut-down
for insufficient VCIN voltage. VDRV supplies the floating high-side drive – consisting of an active boot circuit -
and the low-side drive circuit. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to
prevent false GH turn on during insufficient power supply level condition (BOOT cap charging/discharging
sequence). During undervoltage both GH and GL are driven low actively; further passive pull-down (10 k) is
placed across gate-source of both FETs.
Data Sheet
11 Revision 2.1, 2013-09-05
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet TDA21310.PDF ] | |
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