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PDF LV56351JA Data sheet ( Hoja de datos )
| Número de pieza | LV56351JA | |
| Descripción | 1ch DC/DC boost converter | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA2001
LV56351JA
Bi-CMOS IC
1ch DC/DC boost converter
http://onsemi.com
Overview
LV56351JA integrates 1ch DC/DC boost converter and 1ch LDO. It is suitable as the power supply for BS/CS antennas
of LCD/PDP TV and BD recorders that require automatic recovery without IC destruction and malfunction when the
output is short-circuited.
Functions
DC/DC boost converter
• Soft-start time: 2.8ms
• Frequency 425kHz operation
• Pulse by pulse over current limiter
• Short circuit protector (SCP)
LDO
• Over current limiter (Fold back)
All
• Under voltage lockout
• Thermal shutdown protector
• Power good
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
VCC maximum supply voltage
LDOIN maximum input voltage
SW maximum voltage
Allowable power dissipation
VCC max
VLDOIN
VSW
Pd max
*1
-0.3 to 25
-0.3 to 30
-0.3 to 30
1.1
V
V
V
W
Operating temperature
Topr
-30 to 85
°C
Operating junction temperature Tjopr
-30 to 125
°C
Storage temperature
Tstg
-40 to 150
°C
Allowable
pin
voltage
VCC, EN
SW, LDOIN, LDOOUT
IN1, IN2, FB, SCP, PGOOD, DDCTL
25 V
30 V
6V
*1: When mounted on the specified printed circuit board (32mm × 38mm × 1.6mm), glass epoxy, double side board
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
August, 2013
20112 SY 20111129-S00001 No.A2001-1/8
1 page  
LV56351JA
Continued from preceding page.
Pin No.
17
1
19
20
Pin name
SW
PGND
Function
DC/DC open drain output
Power ground(*3)
VREG
Equivalent circuit
17 SW
1
19 PGND
20
*3: When you use this IC, Please short-circuit all the pins of SGND and PGND on the IC mounting side.
Function overview
(1) UVLO (Under Voltage Lockout)
UVLO stops outputs of both DC/DC and LDO to prevent malfunction when VCC decreases. UVLO operates when
VCC falls below the UVLO voltage. This function is a non-latch-type, and recovers these outputs automatically when
VCC exceeds the UVLO voltage.
(2) Power good
Power good notifies that the output voltages of DC/DC and LDO are within the range of the setting voltage. The two
output voltages are monitored through the voltage of IN1 and IN2. The output is judged to be “power good” when both
outputs are 85% or higher compared to the setting voltages. If either IN1 or IN2 voltage falls below VREF×85%,
PGOOD output becomes L → H (No Good). When IN1 and IN2 voltages become (VREF×85%) + 30mV or higher,
PGOOD output becomes H → L (Good). During soft start, the output is H (No Good).
« Power good circuit diagram »
Power supply (6V or less)
P. Good
Comp.
IN1 +
IN2 +-
(Hysteresis=30mV)
PGOOD
Pin
10kΩ(Example)
Good L output
No Good H output
(3) Pulse-by-Pulse over current protection (P by P)
The P by P stops switch-on operation of a certain cycle by force when the current of power MOSFET reaches the
maximum output peak current.
« P by P circuit diagram »
Error
Amp.
PWM
Comp.
Logic
Power
SW_pin
Triangular wave
P by P
Comp.
The current of power_Tr is
constantly monitored.
If the peak current > 1.8A,
switching_on operation during the
cycle stops compulsorily
(4) Short Circuit Protector (SCP)
When output voltage of DC/DC decreases due to short-circuit; for example, SCP latches off the outputs of DC/DC and
LDO by timer.
When output voltage of DC/DC decreases and FB turns to H, which is the error amplifier output, charge at 4.8μA
constant current starts to SCP capacitor for timer setting. When SCP voltage exceeds the threshold voltage (=VREF),
latch-off occurs. If the output voltage recovers until the time the SCP voltage reaches to the threshold voltage, SCP
capacitor is discharged and timer is reset. To restart the output after latch-off, you need to input EN signal again. If you
do not use the SCP function, make sure to short SCP and GND.
No.A2001-5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LV56351JA.PDF ] | |
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