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Numéro de référence | HMC1031 | ||
Description | 0.1MHz to 500MHz Clock Generator | ||
Fabricant | Analog Devices | ||
Logo | |||
1 Page
Data Sheet
0.1 MHz to 500 MHz Clock Generator
with Integer N PLL
HMC1031
FEATURES
Low current consumption: 1.95 mA typical
High phase frequency detector rate: 140 MHz
Hardware pin-programmable clock multiplication ratios:
1×/5×/10×
Lock detect indicator
Power-down mode (0.8 μA typical)
8-lead MSOP package: 4.9 mm × 3.0 mm
APPLICATIONS
Low jitter clock generation
Low bandwidth (BW) jitter attenuation
Low frequency phase-locked loops (PLLs)
Frequency translation
Oven controlled crystal oscillator (OCXO) frequency
multipliers
Phase lock clean high frequency references to 10 MHz
equipment
GENERAL DESCRIPTION
Together with an external loop filter and a voltage controlled
crystal oscillator (VCXO), the HMC1031 forms a complete
clock generator solution targeted at low frequency jitter
attenuation and reference clock generation applications.
The HMC1031 features a low power integer N divider, support-
ing divide ratios of 1, 5, and 10, which is controlled via external
hardware pins and requires no serial port.
FUNCTIONAL BLOCK DIAGRAM
VCC 1
REFIN 2
HMC1031
PFD/CP
8 GND
7 CP
LKDOP 3
D0 4
LKD 1/N
Figure 1.
6 VCOIN
5 D1
The integrated phase detector and charge pump are capable of
operating at up to 140 MHz, and a maximum VCXO input of
500 MHz ensures frequency compliance with a wide variety of
system clocks and VCXOs.
Additional features include an integrated lock detect indicator
available on a dedicated hardware pin, and a built in power-
down mode.
The HMC1031 is housed in an 8-lead MSOP package.
Rev. C
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Technical Support
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Pages | Pages 13 | ||
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